| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 633 RegisterSubReg DefR(MD); in visitPHI() local
639 if (DefR.SubReg) { in visitPHI()
645 visitUsesOf(DefR.Reg); in visitPHI()
681 visitUsesOf(DefR.Reg); in visitPHI()
703 RegisterSubReg DefR(MO); in visitNonBranch() local
705 if (!DefR.Reg.isVirtual()) in visitNonBranch()
723 visitUsesOf(DefR.Reg); in visitNonBranch()
1935 RegisterSubReg DefR(MD); in evaluate() local
1936 assert(!DefR.SubReg); in evaluate()
1937 if (!DefR.Reg.isVirtual()) in evaluate()
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| H A D | HexagonGenMux.cpp | 108 unsigned DefR, PredR; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
337 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
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| H A D | HexagonConstExtenders.cpp | 1544 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR) in insertInitializer()
1551 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR) in insertInitializer()
1556 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1561 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1570 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR) in insertInitializer()
1583 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1587 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1599 return { DefR, 0 }; in insertInitializer()
1925 Register DefR = insertInitializer(Q.first, P.first); in replaceExtenders() local
1926 NewRegs.push_back(DefR.Reg); in replaceExtenders()
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| H A D | HexagonEarlyIfConv.cpp | 441 Register DefR = MI.getOperand(0).getReg(); in isValid() local
442 if (isPredicate(DefR)) in isValid()
991 Register DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
998 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
1003 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
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| H A D | HexagonBitSimplify.cpp | 1250 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1251 if (!DefR.isVirtual()) in computeUsedBits()
1253 Pending.push_back(DefR); in computeUsedBits()
2954 unsigned DefR; member
2961 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2980 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
3015 unsigned DefR) const { in isBitShuffle()
3167 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" in processLoop()
3195 Register DefR = Defs.find_first(); in processLoop() local
3196 if (!DefR.isVirtual()) in processLoop()
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| H A D | HexagonOptAddrMode.cpp | 97 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
805 Register DefR = MI->getOperand(0).getReg(); in processBlock() local
810 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
834 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
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| H A D | HexagonBitTracker.cpp | 966 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
967 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) { in evaluate()
968 BT::RegisterRef PD(DefR, 0); in evaluate()
971 RegisterCell RC = RegisterCell::self(DefR, RW); in evaluate()
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