| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineTraceMetrics.cpp | 647 unsigned DefOp; member
650 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
651 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
660 DefOp = DefI.getOperandNo(); in DataDep()
754 for (unsigned DefOp : LiveDefOps) { in updatePhysDepsDownwards() local
756 TRI->regunits(UseMI->getOperand(DefOp).getReg().asMCReg())) { in updatePhysDepsDownwards()
759 LRU.Op = DefOp; in updatePhysDepsDownwards()
988 addLiveIns(const MachineInstr *DefMI, unsigned DefOp, in addLiveIns() argument
991 Register Reg = DefMI->getOperand(DefOp).getReg(); in addLiveIns()
1094 addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack); in computeInstrHeights()
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| H A D | PeepholeOptimizer.cpp | 1587 MachineOperand &DefOp = MI.getOperand(0); in findTargetRecurrence() local
1588 if (!isVirtualRegisterOperand(DefOp)) in findTargetRecurrence()
1600 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC); in findTargetRecurrence()
1606 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC); in findTargetRecurrence()
1913 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast() local
1914 if (DefOp.getSubReg() != DefSubReg) in getNextSourceFromBitcast()
1942 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) { in getNextSourceFromBitcast()
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| H A D | SplitKit.cpp | 455 for (const MachineOperand &DefOp : DefMI->defs()) { in addDeadDef() local
456 Register R = DefOp.getReg(); in addDeadDef()
459 if (unsigned SR = DefOp.getSubReg()) in addDeadDef()
1384 const MachineOperand &DefOp = MI->getOperand(DefOpIdx); in rewriteAssigned() local
1385 IsEarlyClobber = DefOp.isEarlyClobber(); in rewriteAssigned()
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| H A D | MachineSink.cpp | 312 auto *DefOp = PI->findRegisterDefOperand(Reg, false, true, TRI); in INITIALIZE_PASS_DEPENDENCY() local
313 if (DefOp && !DefOp->isDead()) in INITIALIZE_PASS_DEPENDENCY()
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| H A D | MachinePipeliner.cpp | 424 MachineOperand &DefOp = PI.getOperand(0); in preprocessPhiNodes() local
425 assert(DefOp.getSubReg() == 0); in preprocessPhiNodes()
426 auto *RC = MRI.getRegClass(DefOp.getReg()); in preprocessPhiNodes()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 1205 if (const MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) { in isEFLAGSDefLive() local
1206 return !DefOp->isDead(); in isEFLAGSDefLive()
1216 if (MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) { in isEFLAGSLive() local
1218 if (DefOp->isDead()) in isEFLAGSLive()
1954 auto &DefOp = MI.getOperand(0); in hardenPostLoad() local
1955 Register OldDefReg = DefOp.getReg(); in hardenPostLoad()
1962 DefOp.setReg(UnhardenedReg); in hardenPostLoad()
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| H A D | X86DomainReassignment.cpp | 588 for (auto &DefOp : UseMI.defs()) { in buildClosure() local
589 if (!DefOp.isReg()) in buildClosure()
592 Register DefReg = DefOp.getReg(); in buildClosure()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 228 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
876 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp, in predicateAt() argument
907 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineTraceMetrics.h | 344 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 718 MachineOperand &DefOp = Def->getOperand(1); in tryToFoldACImm() local
719 if (DefOp.isImm() && TII->isInlineConstant(DefOp, OpTy) && in tryToFoldACImm()
720 TII->isOperandLegal(*UseMI, UseOpIdx, &DefOp)) { in tryToFoldACImm()
721 UseMI->getOperand(UseOpIdx).ChangeToImmediate(DefOp.getImm()); in tryToFoldACImm()
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| H A D | SIInstrInfo.cpp | 660 MachineOperand &DefOp = Def->getOperand(1); in indirectCopyToAGPR() local
661 assert(DefOp.isReg() || DefOp.isImm()); in indirectCopyToAGPR()
663 if (DefOp.isReg()) { in indirectCopyToAGPR()
668 if (I->modifiesRegister(DefOp.getReg(), &RI)) in indirectCopyToAGPR()
674 DefOp.setIsKill(false); in indirectCopyToAGPR()
679 .add(DefOp); in indirectCopyToAGPR()
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