| /freebsd-14.2/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | snps,dw-wdt.yaml | 40 description: DW Watchdog pre-timeout interrupt 56 description: Phandle to the DW Watchdog reset lane 62 DW APB Watchdog custom timer intervals - Timeout Period ranges (TOPs). 66 the timer expiration intervals supported by the DW APB Watchdog. Note 67 DW APB Watchdog IP-core might be synthesized with fixed TOP values,
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| /freebsd-14.2/sys/contrib/device-tree/src/arc/ |
| H A D | axc003.dtsi | 120 * The DW APB ICTL intc on MB is connected to CPU intc via a 121 * DT "invisible" DW APB GPIO block, configured to simply pass thru 125 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core) 126 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
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| H A D | axs10x_mb.dtsi | 55 * DW sdio controller has external ciu clock divider 103 * According to DW Mobile Storage databook it is required 116 * "snps,dw-mshc" should be enough for all users of DW MMC once
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| H A D | axc001.dtsi | 83 * This INTC is actually connected to DW APB GPIO
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| H A D | axc003_idu.dtsi | 127 * This INTC is actually connected to DW APB GPIO
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| H A D | hsdk.dts | 157 * DW sdio controller has external ciu clock divider
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | snps,dw-umctl2-ddrc.yaml | 20 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a 28 description: Synopsys DW uMCTL2 DDR controller v3.80a 30 - description: Synopsys DW uMCTL2 DDR controller 37 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Context.h | 34 PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS, 38 DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS), in MicroOpQueueSize()
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/reset/ |
| H A D | snps,axs10x-reset.txt | 4 to control reset signals of selected peripherals. For example DW GMAC, etc... 9 - DW GMAC - line 5
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| H A D | snps,axs10x-reset.yaml | 14 to control reset signals of selected peripherals. For example DW GMAC, etc... 18 - DW GMAC - line 5
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/bus/ |
| H A D | baikal,bt1-axi.yaml | 16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so 22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/DebugInfo/MSF/ |
| H A D | MSFBuilder.cpp | 405 BinaryStreamWriter DW(*DirStream); in commit() local 406 if (auto EC = DW.writeInteger<uint32_t>(Layout.StreamSizes.size())) in commit() 409 if (auto EC = DW.writeArray(Layout.StreamSizes)) in commit() 413 if (auto EC = DW.writeArray(Blocks)) in commit()
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/spi/ |
| H A D | renesas,rzn1-spi.txt | 3 This controller is based on the Synopsys DW Synchronous Serial Interface and
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| H A D | snps,dw-apb-ssi.yaml | 55 - description: Generic DW SPI Controller 95 - description: DW APB SSI controller memory mapped registers
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 640 const uint32_t DW = eatBytes<uint32_t>(Bytes); in getInstruction() local 641 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); in getInstruction() 644 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); in getInstruction() 647 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); in getInstruction() 651 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); in getInstruction() 657 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); in getInstruction() 661 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); in getInstruction() 664 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, in getInstruction() 668 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, in getInstruction() 674 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; in getInstruction()
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | snps,dw-apb-timers-pwm2.yaml | 8 title: Synopsys DW-APB timers PWM controller
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfUnit.h | 77 DwarfDebug *DW, DwarfFile *DWU, unsigned UniqueID = 0); 383 DwarfTypeUnit(DwarfCompileUnit &CU, AsmPrinter *A, DwarfDebug *DW,
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| H A D | DwarfCompileUnit.cpp | 45 static dwarf::Tag GetCompileUnitType(UnitKind Kind, DwarfDebug *DW) { in GetCompileUnitType() argument 52 if (DW->getDwarfVersion() >= 5 && Kind == UnitKind::Skeleton) in GetCompileUnitType() 59 AsmPrinter *A, DwarfDebug *DW, in DwarfCompileUnit() argument 61 : DwarfUnit(GetCompileUnitType(Kind, DW), Node, A, DW, DWU, UID) { in DwarfCompileUnit()
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| H A D | DwarfCompileUnit.h | 144 DwarfDebug *DW, DwarfFile *DWU,
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| H A D | DwarfUnit.cpp | 83 AsmPrinter *A, DwarfDebug *DW, DwarfFile *DWU, in DwarfUnit() argument 85 : DIEUnit(UnitTag), UniqueID(UniqueID), CUNode(Node), Asm(A), DD(DW), in DwarfUnit() 89 DwarfDebug *DW, DwarfFile *DWU, unsigned UniqueID, in DwarfTypeUnit() argument 91 : DwarfUnit(dwarf::DW_TAG_type_unit, CU.getCUNode(), A, DW, DWU, UniqueID), in DwarfTypeUnit()
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | snps,dw-apb-gpio.yaml | 38 - description: DW GPIO debounce reference clock source
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | snps,designware-i2c.yaml | 40 - description: DW APB I2C controller memory mapped registers
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsScheduleGeneric.td | 1588 def : InstRW<[GenericWriteFPUL], (instregex "^FADD_[DW]$")>; 1589 def : InstRW<[GenericWriteFPUL], (instregex "^FMADD_[DW]$")>; 1590 def : InstRW<[GenericWriteFPUL], (instregex "^FMSUB_[DW]$")>; 1591 def : InstRW<[GenericWriteFPUL], (instregex "^FMUL_[DW]$")>; 1592 def : InstRW<[GenericWriteFPUL], (instregex "^FRCP_[DW]$")>; 1593 def : InstRW<[GenericWriteFPUL], (instregex "^FRSQRT_[DW]$")>; 1594 def : InstRW<[GenericWriteFPUL], (instregex "^FSQRT_[DW]$")>; 1595 def : InstRW<[GenericWriteFPUL], (instregex "^FSUB_[DW]$")>; 1596 def : InstRW<[GenericWriteFPUL], (instregex "^FDIV_[DW]$")>;
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/dma/ |
| H A D | snps,dma-spear1340.yaml | 108 bits, which is impossible in accordance with DW DMAC IP-core data book.
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/pci/ |
| H A D | snps,dw-pcie-ep.yaml | 82 the DW PCIe slave interface.
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