| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUImageIntrinsicOptimizer.cpp | 203 ConstantInt *DMask = cast<ConstantInt>( in optimizeSection() local
205 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in optimizeSection()
242 ConstantInt::get(DMask->getType(), NewMaskVal); in optimizeSection()
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| H A D | MIMGInstructions.td | 423 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
436 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
460 (ins SReg_256:$srsrc, DMask:$dmask,
485 (ins SReg_256:$srsrc, DMask:$dmask,
512 (ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
701 (ins SReg_256:$srsrc, DMask:$dmask,
727 (ins SReg_256:$srsrc, DMask:$dmask,
858 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
870 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
918 (ins SReg_256:$srsrc, DMask:$dmask,
[all …]
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| H A D | SILoadStoreOptimizer.cpp | 115 unsigned DMask; member
182 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()
758 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
908 unsigned MaxMask = std::max(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
909 unsigned MinMask = std::min(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
1365 unsigned MergedDMask = CI.DMask | Paired.DMask; in mergeImagePair()
1827 assert(((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == Width) && in getNewOpcode()
1837 ((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == in getSubRegIdxs()
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| H A D | AMDGPUInstCombineIntrinsic.cpp | 1275 ConstantInt *DMask = cast<ConstantInt>(Args[DMaskIdx]); in simplifyAMDGCNMemoryIntrinsicDemanded() local
1276 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in simplifyAMDGCNMemoryIntrinsicDemanded()
1297 Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal); in simplifyAMDGCNMemoryIntrinsicDemanded()
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| H A D | AMDGPUInstructionSelector.cpp | 1866 unsigned DMask = 0; in selectImageIntrinsic() local
1882 DMask = Is64Bit ? 0xf : 0x3; in selectImageIntrinsic()
1885 DMask = Is64Bit ? 0x3 : 0x1; in selectImageIntrinsic()
1889 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in selectImageIntrinsic()
1890 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in selectImageIntrinsic()
2028 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
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| H A D | AMDGPULegalizerInfo.cpp | 6130 unsigned DMask = 0; in legalizeImageIntrinsic() local
6150 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in legalizeImageIntrinsic()
6153 } else if (DMask != 0) { in legalizeImageIntrinsic()
6154 DMaskLanes = llvm::popcount(DMask); in legalizeImageIntrinsic()
6177 if (IsTFE && DMask == 0) { in legalizeImageIntrinsic()
6178 DMask = 0x1; in legalizeImageIntrinsic()
6180 MI.getOperand(ArgOffset + Intr->DMaskIndex).setImm(DMask); in legalizeImageIntrinsic()
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| H A D | SIISelLowering.cpp | 1202 unsigned DMask in getTgtMemIntrinsic() local
1204 MaxNumLanes = DMask == 0 ? 1 : llvm::popcount(DMask); in getTgtMemIntrinsic()
1218 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue(); in getTgtMemIntrinsic() local
1219 unsigned DMaskLanes = DMask == 0 ? 1 : llvm::popcount(DMask); in getTgtMemIntrinsic()
7485 unsigned DMask; in lowerImage() local
7504 DMask = Is64Bit ? 0xf : 0x3; in lowerImage()
7507 DMask = Is64Bit ? 0x3 : 0x1; in lowerImage()
7511 DMask = Op->getConstantOperandVal(ArgOffset + Intr->DMaskIndex); in lowerImage()
7512 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in lowerImage()
7695 DMask = 0x1; in lowerImage()
[all …]
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| H A D | SIInstrInfo.cpp | 4748 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask); in verifyInstruction() local
4749 if (DMask) { in verifyInstruction()
4750 uint64_t DMaskImm = DMask->getImm(); in verifyInstruction()
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| H A D | SIInstrInfo.td | 1078 def DMask : NamedIntOperand<i16, "dmask">;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3709 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGDataSize() local
3710 if (DMask == 0) in validateMIMGDataSize()
3711 DMask = 1; in validateMIMGDataSize()
3715 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask); in validateMIMGDataSize()
3816 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGAtomicDMask() local
3822 return DMask == 0x1 || DMask == 0x3 || DMask == 0xf; in validateMIMGAtomicDMask()
3834 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGGatherDMask() local
3841 return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8; in validateMIMGGatherDMask()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 1099 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; in convertMIMGInst() local
1100 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); in convertMIMGInst()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 882 // Marker class for intrinsics with a DMask that determines the returned
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 40525 int DMask[] = {0, 1, 2, 3}; in combineTargetShuffle() local
40527 DMask[DOffset + 0] = DOffset + 1; in combineTargetShuffle()
40528 DMask[DOffset + 1] = DOffset + 0; in combineTargetShuffle()
40532 getV4X86ShuffleImm8ForMask(DMask, DL, DAG)); in combineTargetShuffle()
40547 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D); in combineTargetShuffle() local
40558 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2; in combineTargetShuffle()
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