| /freebsd-14.2/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
13 DMA channels and the address space of the DMA controller
17 - DMA channel nodes:
68 ** Freescale EloPlus DMA Controller
81 DMA channels and the address space of the DMA controller
83 - DMA channel nodes:
128 ** Freescale Elo3 DMA Controller
140 DMA channels and the address space of the DMA controller
142 - DMA channel nodes:
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/dma/ |
| H A D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
10 - reg : Should contain DMA registers location and length
12 should contain DMA Error interrupt
16 - dma-channels : Number of DMA channels supported. Should be 16.
18 - dma-requests : Number of DMA requests supported.
32 * DMA client
34 Clients have to specify the DMA requests with phandles in a list.
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| H A D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
18 when mapping xbar input to DMA request, they are either
24 the DMA event number as crossbar ID (input to the DMA crossbar).
33 /* DMA controller */
46 /* DMA crossbar */
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| H A D | st,stm32-dma.yaml | 7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
17 3. A 32bit mask specifying the DMA channel configuration which are device
34 -bit 0-1: DMA FIFO threshold selection
39 -bit 2: DMA direct mode
41 0x1: Direct mode: each DMA request immediately initiates a transfer
43 -bit 4: alternative DMA request/acknowledge protocol
73 description: Should contain all of the per-channel DMA
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| H A D | renesas,shdma.txt | 3 Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
12 * DMA multiplexer
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
22 * DMA controller
73 * DMA client
76 - dmas: a list of <[DMA multiplexer phandle] [MID/RID value]> pairs,
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| H A D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
29 DMA clients must use the format described in dma/dma.txt file.
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| H A D | sprd-dma.txt | 1 * Spreadtrum DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
7 - reg: Should contain DMA registers location and length.
11 - dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
16 - #dma-channels : Number of DMA channels supported. Should be 32.
33 DMA clients connected to the Spreadtrum DMA controller must use the format
36 1. A phandle pointing to the DMA controller.
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| H A D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - dma-channels: Number of DMA channels supported by the controller (defaults
16 - dma-requests: Number of DMA requestor lines supported by the controller
28 * while DMA controller may not able to distinguish the irq channel
43 * Dmaengine driver (DMA controller) distinguish irq channel via
54 Marvell Two Channel DMA Controller used specifically for audio
59 - reg: Should contain DMA registers location and length.
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| H A D | intel,ldma.yaml | 7 title: Lightning Mountain centralized DMA controllers.
34 The first cell is the peripheral's DMA request line.
61 DMA descriptor polling counter is used to control the poling mechanism
67 DMA byte enable is only valid for DMA write(RX).
68 Byte enable(1) means DMA write will be based on the number of dwords
74 DMA descriptor read back to make sure data and desc synchronization.
79 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
80 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
81 It only applies to RX DMA and memcopy DMA.
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| H A D | dma-common.yaml | 7 title: DMA Engine Common Properties
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
25 Used to provide DMA controller specific information.
29 Bitmask of available DMA channels in ascending order that are
43 Number of DMA channels supported by the controller.
48 Number of DMA request signals supported by the controller.
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| H A D | owl-dma.txt | 1 * Actions Semi Owl SoCs DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
7 - reg: Should contain DMA registers location and length.
12 - dma-requests: Number of DMA request signals supported by the controller.
14 - clocks: Phandle and Specifier of the clock feeding the DMA controller.
34 DMA clients connected to the Actions Semi Owl SoCs DMA controller must
39 1. A phandle pointing to the DMA controller.
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| H A D | dma-router.yaml | 7 title: DMA Router Common Properties
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
30 Array of phandles to the DMA controllers the router can direct
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| H A D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
6 Required properties for DMA interfaces:
11 1st - DMA control and status register address space.
15 - interrupts: DMA has 5 interrupts sources. 1st interrupt is
16 DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
17 are completion interrupts for each DMA channels.
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| H A D | snps,dma-spear1340.yaml | 7 title: Synopsys Designware DMA Controller
30 First cell is a phandle pointing to the DMA controller. Second one is
31 the DMA request line number. Third cell is the memory master identifier
52 Number of DMA channels supported by the controller. In case if
65 Number of DMA masters supported by the controller. In case if
74 DMA channels allocation order specifier. Zero means ascending order
82 DMA channels priority order. Zero means ascending channels priority
90 description: Maximum block size supported by the DMA controller.
95 description: Data bus width per each DMA master in bytes.
125 each DMA channel.
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| H A D | atmel-dma.txt | 1 * Atmel Direct Memory Access Controller (DMA)
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain DMA interrupt.
19 DMA clients connected to the Atmel DMA controller must use the format
24 1. A phandle pointing to the DMA controller.
27 3. Parameters for the at91 DMA configuration register which are device
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| H A D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
31 - adi,length-width: Width of the DMA transfer length register.
32 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
34 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
38 specifier refers to the DMA channel index.
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| H A D | milbeaut-m10v-xdmac.txt | 1 * Milbeaut AXI DMA Controller
3 Milbeaut AXI DMA controller has only memory to memory transfer capability.
5 * DMA controller
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain all of the per-channel DMA interrupts.
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| H A D | renesas,rz-dmac.yaml | 7 title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
27 - description: DMA extended resource selector block
54 - description: DMA main clock
55 - description: DMA register access clock
66 connected to the DMA client and the slave channel configuration
69 bit[10] - Specifies DMA request high enable (HIEN)
70 bit[11] - Specifies DMA request detection type (LVL)
82 - description: Reset for DMA ARESETN reset terminal
83 - description: Reset for DMA RST_ASYNC reset terminal
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| H A D | nvidia,tegra20-apbdma.txt | 1 * NVIDIA Tegra APB DMA controller
5 - reg: Should contain DMA registers location and length. This shuld include
7 - interrupts: Should contain all of the per-channel DMA interrupts.
14 - #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
15 client nodes' dmas properties. The specifier represents the DMA request
17 documentation of the APB DMA channel control register REQ_SEL field.
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| H A D | brcm,bcm2835-dma.txt | 1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
70 DMA clients connected to the BCM2835 DMA controller must use the format
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| H A D | owl-dma.yaml | 7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
33 DMA channels.
48 Phandle and Specifier of the clock feeding the DMA controller.
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| H A D | fsl-mxs-dma.txt | 1 * Freescale MXS DMA
6 - interrupts : Should contain the interrupt numbers of DMA channels.
9 - dma-channels : Number of channels supported by the DMA controller
12 - interrupt-names : Name of DMA channel interrupts
49 DMA clients connected to the MXS DMA controller must use the format
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
34 into DMA and the DMA uses it as the physical addresses to reach queue
40 DMA instance properties:
94 Navigator DMA client:
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/powerpc/4xx/ |
| H A D | ppc440spe-adma.txt | 1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
4 are specified hereby. These are I2O/DMA, DMA and XOR nodes
5 for DMA engines and Memory Queue Module node. The latter is used
9 DMA devices.
28 ii) The DMA node
33 - cell-index : 1 cell, hardware index of the DMA engine
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/spi/ |
| H A D | omap-spi.txt | 15 - dmas: List of DMA specifiers with the controller specific format
16 as described in the generic DMA client binding. A tx and rx
18 - dma-names: List of DMA request names. These strings correspond
19 1:1 with the DMA specifiers listed in dmas. The string naming
25 [hwmod populated DMA resources]
35 [generic DMA request binding]
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