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/freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsynopsys.txt3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16 - reg: Should contain DDR controller registers location and length.
H A Dsnps,dw-umctl2-ddrc.yaml15 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
20 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
28 description: Synopsys DW uMCTL2 DDR controller v3.80a
30 - description: Synopsys DW uMCTL2 DDR controller
32 - description: Xilinx ZynqMP DDR controller v2.40a
H A Dath79-ddr-controller.txt1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
H A Dqca,ath79-ddr-controller.yaml7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
H A Drockchip,rk3399-dmc.yaml20 Node to get DDR loading. Refer to
44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
318 Defines the power-down idle disable frequency in Hz. When the DDR
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
331 frequency in Hz. When the DDR frequency is greater than
[all …]
H A Dxlnx,zynq-ddrc-a05.yaml7 title: Zynq A05 DDR Memory Controller
15 The Zynq DDR ECC controller has an optional ECC support in half-bus width
H A Dcalxeda-ddr-ctrlr.yaml7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
H A Dbrcm,dpfe-cpu.txt1 DDR PHY Front End (DPFE) for Broadcom STB
5 communicate with the DCPU, which resides inside the DDR PHY.
H A Drenesas,dbsc.yaml7 title: Renesas DDR Bus Controllers
15 different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
H A Dsynopsys,ddrc-ecc.yaml15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
18 The Zynq DDR ECC controller has an optional ECC support in half-bus width
/freebsd-14.2/sys/contrib/device-tree/Bindings/mips/brcm/
H A Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
95 - reg : the DDR PHY register range and length
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
136 - reg : the DDR Arbiter register range and length
/freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/fsl/
H A Dddr.txt1 Freescale DDR memory controller
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
H A Dmmdc.txt1 Freescale Multi Mode DDR controller (MMDC)
19 - reg : address and size of MMDC DDR controller registers
H A Dimx8m-ddrc.yaml7 title: i.MX8M DDR Controller
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-core-clock.txt12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
H A Dbrcm,bcm2835-cprman.txt27 - DSI0 DDR clock
30 - DSI1 DDR clock
/freebsd-14.2/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
179 Control registers for this memory controller's DDR SHIMPHY.
183 - reg : the DDR SHIMPHY register range
185 == MEMC DDR control
/freebsd-14.2/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt5 - devfreq-events: Node to get DDR loading, Refer to
21 It should be a DCF interrupt. When DDR DVFS finishes
26 Following properties relate to DDR timing:
65 When DDR frequency is less than DRAM_DLL_DISB_FREQ,
70 MHz (Mega Hz). When DDR frequency is less than
76 when the DDR frequency is less then ddr3_odt_dis_freq,
102 When DDR frequency is less then ddr3_odt_dis_freq,
128 MHz (Mega Hz). When the DDR frequency is less then
/freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Dlpddr3-timings.txt7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
H A Dlpddr2-timings.txt5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
H A Djedec,lpddr3-timings.yaml19 Maximum DDR clock frequency for the speed-bin, in Hz.
26 Maximum DDR clock frequency for the speed-bin, in Hz.
31 Minimum DDR clock frequency for the speed-bin, in Hz.
/freebsd-14.2/sys/contrib/device-tree/Bindings/ddr/
H A Dlpddr3-timings.txt7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
H A Dlpddr2-timings.txt5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
/freebsd-14.2/sys/contrib/device-tree/Bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml7 title: Amlogic G12 DDR performance monitor
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
/freebsd-14.2/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx7ulp-pinctrl.txt4 ports and IOMUXC DDR for DDR interface.

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