| /freebsd-14.2/sys/contrib/openzfs/include/os/freebsd/spl/sys/ia32/ |
| H A D | asm_linkage.h | 60 #define D16 data16; macro 76 #define D16 .byte 0x66;
|
| /freebsd-14.2/sys/contrib/openzfs/lib/libspl/include/os/freebsd/sys/ia32/ |
| H A D | asm_linkage.h | 63 #define D16 data16; macro 79 #define D16 .byte 0x66;
|
| /freebsd-14.2/sys/contrib/openzfs/include/os/linux/spl/sys/ia32/ |
| H A D | asm_linkage.h | 81 #define D16 data16; macro 97 #define D16 .byte 0x66;
|
| /freebsd-14.2/sys/contrib/openzfs/lib/libspl/include/os/linux/sys/ia32/ |
| H A D | asm_linkage.h | 81 #define D16 data16; macro 97 #define D16 .byte 0x66;
|
| /freebsd-14.2/contrib/opencsd/decoder/include/opencsd/stm/ |
| H A D | trc_pkt_elem_stm.h | 152 payload.D16 = value; in setD16Payload() 217 return payload.D16; in getD16Val()
|
| H A D | trc_pkt_types_stm.h | 117 …uint16_t D16; /**< payload for D16 data packet, or reserved opcode in bad packet header (1-3 nib… member
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | ARMTargetParser.cpp | 172 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16}, in getFPUFeatures() 175 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16}, in getFPUFeatures() 180 {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16}, in getFPUFeatures() 184 {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16}, in getFPUFeatures() 188 {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16}, in getFPUFeatures()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | MIMGInstructions.td | 425 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 438 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 450 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 463 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 475 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 488 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 500 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 515 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 664 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 678 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); [all …]
|
| H A D | SIInstrFormats.td | 119 // This bit indicates that this is a D16 buffer instruction.
|
| /freebsd-14.2/lib/msun/ld128/ |
| H A D | s_expl.c | 195 D16 = 4.7628892832607741e-14, /* 0x1.ad00Dfe41feccp-45 */ variable 252 dx * (D14 + dx * (D15 + dx * (D16 + in expm1l()
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/TargetParser/ |
| H A D | ARMTargetParser.def | 24 ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FPUVersion::VFPV3, NeonSupportLevel::None, FPURestriction::D16) 25 …-d16-fp16", FK_VFPV3_D16_FP16, FPUVersion::VFPV3_FP16, NeonSupportLevel::None, FPURestriction::D16) 29 ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FPUVersion::VFPV4, NeonSupportLevel::None, FPURestriction::D16) 31 ARM_FPU("fpv5-d16", FK_FPV5_D16, FPUVersion::VFPV5, NeonSupportLevel::None, FPURestriction::D16) 34 … FK_FP_ARMV8_FULLFP16_D16, FPUVersion::VFPV5_FULLFP16, NeonSupportLevel::None, FPURestriction::D16)
|
| H A D | ARMTargetParser.h | 142 D16, ///< Only 16 D registers enumerator
|
| /freebsd-14.2/contrib/opencsd/decoder/source/stm/ |
| H A D | trc_pkt_elem_stm.cpp | 139 oss << "; Data=0x" << std::hex << std::setw(4) << std::setfill('0') << payload.D16; in toString()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 112 case D19: case D18: case D17: case D16: in isARMArea3Register()
|
| H A D | ARMRegisterInfo.td | 140 def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>; 169 def Q8 : ARMReg< 8, "q8", [D16, D17]>; 448 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on 520 // Allocate starting at non-VFP2 registers D16-D31 first.
|
| H A D | ARMBaseRegisterInfo.cpp | 219 static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!"); in getReservedRegs() 221 markSuperRegs(Reserved, ARM::D16 + R); in getReservedRegs()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.cpp | 90 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()
|
| H A D | SparcRegisterInfo.td | 263 def D16 : SparcReg< 1, "f32">; 289 def Q8 : Rq< 1, "f32", [D16, D17]>;
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 147 case AArch64::D16: return AArch64::B16; in getBRegFromDReg() 187 case AArch64::B16: return AArch64::D16; in getDRegFromBReg()
|
| /freebsd-14.2/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am642-phyboard-electra-rdk.dts | 169 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 120 case AArch64::D16: in isOdd()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 81 SP::D0, SP::D16, SP::D1, SP::D17,
|
| /freebsd-14.2/sys/contrib/device-tree/src/arm/ |
| H A D | am335x-boneblue.dts | 454 "UART1_RX", /* D16 */
|
| H A D | am335x-guardian.dts | 502 /* (D16) uart1_rxd.uart1_rxd */
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 296 {codeview::RegisterId::ARM_ND16, ARM::D16}, in initLLVMToCVRegMapping()
|