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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP10InstrResources.td1172 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands
1212 // 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU oper…
1340 // 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load …
1347 // 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load …
1412 // 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations…
1419 // 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations…
1552 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix…
1892 …Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operatio…
1900 // 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, and 3 Cycles Stor…
1908 // 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles St…
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp44 unsigned int Cycles = 0; member
48 : HasReturn(HasReturn), Cycles(Cycles) {} in VisitedBBInfo()
75 unsigned int Cycles = 0);
78 unsigned int &Cycles);
133 unsigned Cycles = ReturnBB.second; in runOnMachineFunction() local
140 if (Cycles < Threshold) { in runOnMachineFunction()
166 if (Cycles >= Threshold) in findReturns()
177 findReturns(Succ, Cycles); in findReturns()
191 Cycles += BBInfo.Cycles; in cyclesUntilReturn()
203 Cycles += CyclesToEnd; in cyclesUntilReturn()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp22 unsigned Cycles) { in writeStartEvent() argument
25 CRD.Cycles = Cycles; in writeStartEvent()
26 DependentWriteCyclesLeft = Cycles; in writeStartEvent()
31 unsigned Cycles) { in writeStartEvent() argument
41 if (TotalCycles < Cycles) { in writeStartEvent()
44 CRD.Cycles = Cycles; in writeStartEvent()
45 TotalCycles = Cycles; in writeStartEvent()
132 if (CriticalRegDep.Cycles) in computeCriticalRegDep()
138 if (WriteCRD.Cycles > MaxLatency) in computeCriticalRegDep()
144 if (ReadCRD.Cycles > MaxLatency) in computeCriticalRegDep()
H A DPipeline.cpp46 ++Cycles; in run()
49 return Cycles; in run()
97 LLVM_DEBUG(dbgs() << "\n[E] Cycle begin: " << Cycles << '\n'); in notifyCycleBegin()
103 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n"); in notifyCycleEnd()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFive7.td479 …let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in…
499 …let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in…
516 …let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in…
533 …let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in…
574 …let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in…
641 …let Latency = !add(Cycles, 3), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in…
659 let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
744 …let Latency = !add(Cycles, 3), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in…
754 let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
806 let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp113 DelayInfo(DelayType Type, unsigned Cycles) { in DelayInfo()
118 VALUCycles = Cycles; in DelayInfo()
122 TRANSCycles = Cycles; in DelayInfo()
157 bool advance(DelayType Type, unsigned Cycles) { in advance()
167 VALUCycles -= Cycles; in advance()
180 TRANSCycles -= Cycles; in advance()
184 if (SALUCycles <= Cycles) { in advance()
189 SALUCycles -= Cycles; in advance()
230 void advance(DelayType Type, unsigned Cycles) { in advance()
234 if (I->second.advance(Type, Cycles)) in advance()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h87 int16_t Cycles; member
91 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
106 int Cycles; member
110 && Cycles == Other.Cycles;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h119 unsigned Cycles = IR.getInstruction()->getCyclesLeft(); in onGroupIssued() local
120 if (CriticalPredecessor.Cycles < Cycles) { in onGroupIssued()
122 CriticalPredecessor.Cycles = Cycles; in onGroupIssued()
184 if (isWaiting() && CriticalPredecessor.Cycles) in cycleEvent()
185 CriticalPredecessor.Cycles--; in cycleEvent()
/freebsd-14.2/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DTimelineView.cpp22 unsigned Cycles) in TimelineView() argument
24 MaxCycle(Cycles == 0 ? std::numeric_limits<unsigned>::max() : Cycles), in TimelineView()
121 static void tryChangeColor(raw_ostream &OS, unsigned Cycles, in tryChangeColor() argument
126 raw_ostream::Colors Color = chooseColor(Cycles, Executions, BufferSize); in tryChangeColor()
257 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) { in printTimelineHeader() argument
259 if (Cycles >= 10) { in printTimelineHeader()
261 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
272 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
H A DBottleneckAnalysis.cpp506 unsigned Cycles = 2 * Tracker.getResourcePressureCycles(IID); in onEvent() local
513 addResourceDep(U.first % Source.size(), To, Current, U.second + Cycles); in onEvent()
519 if (RegDep.Cycles) { in onEvent()
520 Cycles = RegDep.Cycles + 2 * Tracker.getRegisterPressureCycles(IID); in onEvent()
522 addRegisterDep(From, To, RegDep.RegID, Cycles); in onEvent()
526 if (MemDep.Cycles) { in onEvent()
527 Cycles = MemDep.Cycles + 2 * Tracker.getMemoryPressureCycles(IID); in onEvent()
529 addMemoryDep(From, To, Cycles); in onEvent()
H A DTimelineView.h167 unsigned Cycles);
/freebsd-14.2/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp32 unsigned Cycles = Resource.second.size(); in execute() local
41 std::make_pair(ResourceUnit, ReleaseAtCycles(Cycles, NumUnits))); in execute()
57 ReleaseAtCycles(Cycles, NumUnits * SubUnit.NumUnits))); in execute()
H A DInOrderIssueStage.cpp30 void StallInfo::update(const InstRef &Inst, unsigned Cycles, StallKind SK) { in update() argument
32 CyclesLeft = Cycles; in update()
119 if (unsigned Cycles = checkRegisterHazard(PRF, STI, IR)) { in canExecute() local
120 SI.update(IR, Cycles, StallInfo::StallKind::REGISTER_DEPS); in canExecute()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp857 struct Cycles { struct
936 << Cycles{"ResLength", ResLength} in shouldConvertIf()
939 << Cycles{"CritLimit", CritLimit} in shouldConvertIf()
1025 << Cycles{"ShortCycles", Short.Extra}; in shouldConvertIf()
1028 << Cycles{"LongCycles", Long.Extra}; in shouldConvertIf()
1030 << Cycles{"CritLimit", CritLimit} << "."; in shouldConvertIf()
1043 << Cycles{"ShortCycles", Short.Extra}; in shouldConvertIf()
1049 << Cycles{"LongCycles", Long.Extra}; in shouldConvertIf()
1169 unsigned Cycles = 0; in shouldConvertIf() local
1173 Cycles += NumCycles - 1; in shouldConvertIf()
[all …]
H A DTargetSchedule.cpp114 static unsigned capLatency(int Cycles) { in capLatency() argument
115 return Cycles >= 0 ? Cycles : 1000; in capLatency()
208 unsigned Latency = capLatency(WLEntry->Cycles); in computeOperandLatency()
H A DMachineTraceMetrics.cpp601 Cycles.erase(&I); in invalidate()
788 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
813 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in updateDepth()
821 InstrCycles &MICycles = Cycles[&UseMI]; in updateDepth()
1090 unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0; in computeInstrHeights()
1126 InstrCycles &MICycles = Cycles[&MI]; in computeInstrHeights()
1241 unsigned Cycles = 0; in getResourceLength() local
1251 Cycles += (PI->ReleaseAtCycle * in getResourceLength()
1255 return Cycles; in getResourceLength()
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp51 if (WLEntry->Cycles < 0) in computeInstrLatency()
52 return WLEntry->Cycles; in computeInstrLatency()
53 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles)); in computeInstrLatency()
165 DelayCycles = std::min(DelayCycles, E.Cycles); in getForwardingDelayCycles()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h188 unsigned Cycles; member
303 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
375 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
419 void subtract(unsigned Cycles) { in subtract() argument
420 assert(End >= Cycles); in subtract()
421 End -= Cycles; in subtract()
439 ResourceUsage(CycleSegment Cycles, unsigned Units = 1)
440 : CS(Cycles), NumUnits(Units) {} in CS()
H A DSupport.h56 ReleaseAtCycles(unsigned Cycles, unsigned ResourceUnits = 1)
57 : Numerator(Cycles), Denominator(ResourceUnits) {} in Numerator() argument
H A DPipeline.h64 unsigned Cycles = 0; variable
/freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dbaikal,bt1-l2-ctl.yaml29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
/freebsd-14.2/sys/contrib/device-tree/Bindings/cache/
H A Dbaikal,bt1-l2-ctl.yaml29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineTraceMetrics.h308 return TE.Cycles.lookup(&MI); in getInstrCycles()
334 DenseMap<const MachineInstr*, InstrCycles> Cycles; variable
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetItinerary.td43 // the execution of an instruction. Cycles represents the number of
52 // InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles
59 int Cycles = cycles; // length of stage in machine cycles
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h50 void update(const InstRef &Inst, unsigned Cycles, StallKind SK);

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