Home
last modified time | relevance | path

Searched refs:Cycle (Results 1 – 25 of 42) sorted by relevance

12

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ADT/
H A DGenericCycleImpl.h151 return Cycle->second;
192 Cycle->appendBlock(Block); in addBlockToCycle()
197 Cycle = ParentCycle; in addBlockToCycle()
198 Cycle->appendBlock(Block); in addBlockToCycle()
309 Cycle->Depth = Cycle->ParentCycle ? Cycle->ParentCycle->Depth + 1 : 1; in updateDepth()
390 if (!Cycle) in splitCriticalEdge()
443 if (!Cycle) in getCycleDepth()
445 return Cycle->getDepth(); in getCycleDepth()
473 check(is_contained(Cycle->ParentCycle->children(), Cycle)); in validateTree()
504 for (const CycleT *Cycle = Entry.second; Cycle; in validateTree() local
[all …]
H A DGenericUniformityImpl.h708 Cycle = Cycle->getParentCycle()) { in computeJoinPoints()
992 assert(Cycle && Cycle->contains(JoinBlock)); in getIntDivCycle()
993 while (Cycle && !Cycle->contains(DivTermBlock)) { in getIntDivCycle()
994 Cycle = Cycle->getParentCycle(); in getIntDivCycle()
996 if (!Cycle || Cycle->isReducible()) in getIntDivCycle()
1023 if (!Cycle) in getOutermostDivergentCycle()
1043 Cycle && !Cycle->contains(&ObservingBlock); in isTemporalDivergent()
1044 Cycle = Cycle->getParentCycle()) { in isTemporalDivergent()
1269 if (Cycle != NestedCycle && (!Cycle || Cycle->contains(NestedCycle))) { in computeStackPO()
1280 if (Cycle && !Cycle->contains(NestedExitBB)) in computeStackPO()
[all …]
H A DGenericCycleInfo.h255 void addBlockToCycle(BlockT *Block, CycleT *Cycle);
281 Printable print(const CycleT *Cycle) { return Cycle->print(Context); } in print() argument
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h91 DenseMap<MachineInstr *, int> Cycle; variable
109 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
111 : Loop(Loop), ScheduledInstrs(ScheduledInstrs), Cycle(std::move(Cycle)), in ModuloSchedule()
128 int getFirstCycle() { return Cycle[ScheduledInstrs.front()]; } in getFirstCycle()
132 int getFinalCycle() { return Cycle[ScheduledInstrs.back()]; } in getFinalCycle()
142 auto I = Cycle.find(MI); in getCycle()
143 return I == Cycle.end() ? -1 : I->second; in getCycle()
H A DMachineCycleAnalysis.h47 bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I);
H A DMachinePipeliner.h476 void reserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
478 void unreserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
514 bool canReserveResources(SUnit &SU, int Cycle);
518 void reserveResources(SUnit &SU, int Cycle);
H A DScheduleDAG.h545 void setCurCycle(unsigned Cycle) { in setCurCycle() argument
546 CurCycle = Cycle; in setCurCycle()
H A DMachineTraceMetrics.h76 unsigned Cycle = 0; member
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td709 // 6 Cycle Load uses a single slice.
1136 // 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1143 // 36 Cycle DP Instruction.
1156 // 36 Cycle DP Vector Instruction.
1163 // 27 Cycle DP Vector Instruction.
1170 // 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1177 // 26 Cycle DP Instruction.
1189 // 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1208 // 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
1296 // Two Cycle Branch
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp805 unsigned Cycle = 0; in updateDepth() local
818 Cycle = std::max(Cycle, DepCycle); in updateDepth()
822 MICycles.Depth = Cycle; in updateDepth()
928 unsigned DepHeight = I->Cycle; in updatePhysDepsUpwards()
948 LRU.Cycle = Height; in updatePhysDepsUpwards()
1046 RegUnits[LI.Reg].Cycle = LI.Height; in computeInstrHeights()
1103 unsigned Cycle = 0; in computeInstrHeights() local
1106 Cycle = HeightI->second; in computeInstrHeights()
1118 Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits, MTM.SchedModel, in computeInstrHeights()
1127 MICycles.Height = Cycle; in computeInstrHeights()
[all …]
H A DMachineCycleAnalysis.cpp94 bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) { in isCycleInvariant() argument
128 } else if (any_of(Cycle->getEntries(), in isCycleInvariant()
145 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent())) in isCycleInvariant()
H A DMachineSink.cpp245 bool SinkIntoCycle(MachineCycle *Cycle, MachineInstr &I);
665 MachineCycle *Cycle, MachineBasicBlock *BB, in FindCycleSinkCandidates() argument
674 if (!isCycleInvariant(Cycle, MI)) { in FindCycleSinkCandidates()
757 for (auto *Cycle : Cycles) { in runOnMachineFunction() local
758 MachineBasicBlock *Preheader = Cycle->getCyclePreheader(); in runOnMachineFunction()
764 FindCycleSinkCandidates(Cycle, Preheader, Candidates); in runOnMachineFunction()
777 if (!SinkIntoCycle(Cycle, *I)) in runOnMachineFunction()
1114 MachineCycle *Cycle = CI->getCycle(DefMI->getParent()); in isProfitableToSinkTo() local
1119 if (Cycle != MCycle || (DefMI->isPHI() && Cycle && Cycle->isReducible() && in isProfitableToSinkTo()
1520 MachineBasicBlock *Preheader = Cycle->getCyclePreheader(); in SinkIntoCycle()
[all …]
H A DMachinePipeliner.cpp652 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in schedule() local
653 ++Cycle) { in schedule()
1030 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in computeScheduledInsts() local
1031 ++Cycle) { in computeScheduledInsts()
1041 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in computeScheduledInsts() local
1042 ++Cycle) { in computeScheduledInsts()
3379 for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) { in finalizeSchedule() local
3539 for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C) in reserveResources()
3542 for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C) in reserveResources()
3551 for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C) in unreserveResources()
[all …]
H A DModuloSchedule.cpp2152 static void parseSymbolString(StringRef S, int &Cycle, int &Stage) { in parseSymbolString() argument
2166 CycleTokenAndValue.second.drop_front().getAsInteger(10, Cycle); in parseSymbolString()
2168 dbgs() << " Stage=" << Stage << ", Cycle=" << Cycle << "\n"; in parseSymbolString()
2176 DenseMap<MachineInstr *, int> Cycle, Stage; in runOnLoop() local
2184 parseSymbolString(Sym->getName(), Cycle[&MI], Stage[&MI]); in runOnLoop()
2188 ModuloSchedule MS(MF, &L, std::move(Instrs), std::move(Cycle), in runOnLoop()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DCycleInfo.h24 using Cycle = CycleInfo::CycleT; variable
/freebsd-14.2/contrib/llvm-project/clang/include/clang/AST/
H A DASTImporter.h169 using Cycle = llvm::iterator_range<VecTy::const_reverse_iterator>; variable
170 Cycle getCycleAtBack() const { in getCycleAtBack()
172 return Cycle(Nodes.rbegin(), in getCycleAtBack()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DUniformityAnalysis.cpp68 const Instruction &I, const Cycle &DefCycle) const { in usesValueFromCycle()
82 const Cycle &DefCycle) { in propagateTemporalDivergence()
/freebsd-14.2/sys/contrib/device-tree/Bindings/regulator/
H A Dpwm-regulator.txt33 - voltage-table: Voltage and Duty-Cycle table consisting of 2 cells
85 /* Voltage Duty-Cycle */
H A Dpwm-regulator.yaml49 description: Voltage and Duty-Cycle table.
118 /* Voltage Duty-Cycle */
/freebsd-14.2/crypto/openssl/doc/life-cycles/
H A DREADME.md1 Algorithm Life-Cycle Diagrams
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp1132 ValueSeq &Cycle) { in findCycle() argument
1153 if (!Cycle.insert(I)) in findCycle()
1155 if (findCycle(I, In, Cycle)) in findCycle()
1157 Cycle.remove(I); in findCycle()
1159 return !Cycle.empty(); in findCycle()
1169 unsigned I, N = Cycle.size(); in classifyCycle()
1171 Value *V = Cycle[I]; in classifyCycle()
1183 First.insert(Cycle[J]); in classifyCycle()
1186 Second.insert(Cycle[I]); in classifyCycle()
1188 Value *V = Cycle[I]; in classifyCycle()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h398 bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; } in contains() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp438 unsigned Cycle = getTransSwizzle(TransSwz, i); in isLegalUpTo() local
443 if (Vector[Src.second][Cycle] < 0) in isLegalUpTo()
444 Vector[Src.second][Cycle] = Src.first; in isLegalUpTo()
445 if (Vector[Src.second][Cycle] != Src.first) in isLegalUpTo()
499 unsigned Cycle = getTransSwizzle(TransSwz, i); in isConstCompatible() local
502 if (ConstCount > 0 && Cycle == 0) in isConstCompatible()
504 if (ConstCount > 1 && Cycle == 1) in isConstCompatible()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h62 void notifyExecuted(unsigned Cycle);
/freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml77 Refresh Cycle time in pico seconds.

12