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Searched refs:Crypto (Results 1 – 25 of 72) sorted by relevance

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/freebsd-14.2/tests/sys/opencrypto/
H A Dcryptotest.py57 crid = cryptodev.Crypto.findcrid(cname)
95 curfun = Crypto.encrypt
98 curfun = Crypto.decrypt
175 curfun = Crypto.encrypt
178 curfun = Crypto.decrypt
207 curfun = Crypto.encrypt
210 curfun = Crypto.decrypt
261 c = Crypto(crid=crid,
265 r, tag = Crypto.encrypt(c, payload,
302 c = Crypto(crid=crid,
[all …]
H A Dcryptodev.py167 class Crypto: class
567 crid = Crypto.findcrid('aesni0')
574 name = Crypto.getcridname(i)
593 c = Crypto(CRYPTO_AES_ICM, key)
614 c = Crypto(CRYPTO_AES_ICM, key)
633 c = Crypto(CRYPTO_AES_CBC, key)
658 c = Crypto(CRYPTO_AES_NIST_GCM_16, key)
694 c = Crypto(CRYPTO_AES_GCM_16, key)
708 …c = Crypto(CRYPTO_AES_XTS, binascii.unhexlify('1bbfeadf539daedcae33ced497343f3ca1f2474ad932b903997…
716 …c = Crypto(CRYPTO_AES_XTS, binascii.unhexlify('1bbfeadf539daedcae33ced497343f3ca1f2474ad932b903997…
[all …]
/freebsd-14.2/sys/contrib/device-tree/Bindings/crypto/
H A Daspeed,ast2500-hace.yaml13 The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
15 divided into two independently engines - Hash Engine and Crypto Engine.
H A Dqcom,inline-crypto-engine.yaml7 title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
H A Dintel,keembay-ocs-aes.yaml13 The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides
H A Dintel,keembay-ocs-hcu.yaml14 The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU)
H A Dintel,keembay-ocs-ecc.yaml14 The Intel Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve
H A Dallwinner,sun8i-ce.yaml7 title: Allwinner Crypto Engine driver
/freebsd-14.2/sys/contrib/device-tree/Bindings/dma/
H A Dste-dma40.txt110 48: Crypto Accelerator 1
111 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
123 61: Crypto Accelerator 0
124 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
H A Dstericsson,dma40.yaml70 48: Crypto Accelerator 1
71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
83 61: Crypto Accelerator 0
84 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
/freebsd-14.2/contrib/xz/
H A DAUTHORS14 code found from Crypto++ <https://www.cryptopp.com/>. The SHA-256 code
15 in Crypto++ was written by Kevin Springle and Wei Dai.
/freebsd-14.2/contrib/ntp/sntp/m4/
H A Dntp_ver_suffix.m42 dnl NTP Version Suffix (Crypto)
/freebsd-14.2/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-msm.yaml74 - description: clock for Inline Crypto Engine
185 - description: Inline Crypto Engine register map
200 - description: Inline Crypto Engine register map
H A Dsdhci-msm.txt38 - Inline Crypto Engine register map (optional)
43 - "ice" for Inline Crypto Engine register map (optional)
56 "ice" - clock for Inline Crypto Engine (optional)
/freebsd-14.2/sys/arm64/conf/
H A Dstd.marvell26 # Crypto accelerators
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA510.td501 // Crypto AES ops
507 // Crypto SHA1 hash acceleration op
511 // Crypto SHA1 hash acceleration ops
512 // Crypto SHA256 hash acceleration ops
518 // Crypto SHA512 hash acceleration ops
521 // Crypto SHA3 ops
526 // Crypto SM3 ops
530 // Crypto SM4 ops
1373 // Crypto AES ops
1377 // Crypto SHA3 ops
[all …]
H A DAArch64SchedNeoverseN2.td1462 // Crypto AES ops
1468 // Crypto SHA1 hash acceleration op
1472 // Crypto SHA1 hash acceleration ops
1473 // Crypto SHA256 hash acceleration ops
1479 // Crypto SHA512 hash acceleration ops
1482 // Crypto SHA3 ops
1485 // Crypto SM3 ops
1489 // Crypto SM4 ops
2289 // Crypto AES ops
2293 // Crypto SHA3 ops
[all …]
/freebsd-14.2/crypto/openssl/providers/implementations/ciphers/
H A Dcipher_aes_gcm_hw_armv8.inc11 * Crypto extention support for AES GCM.
/freebsd-14.2/sys/contrib/device-tree/Bindings/firmware/
H A Dintel,stratix10-svc.txt17 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
/freebsd-14.2/sys/contrib/device-tree/src/powerpc/fsl/
H A Dpq3-sec3.3-0.dtsi2 * PQ3 Sec/Crypto 3.3 device tree stub [ controller @ offset 0x30000 ]
H A Dpq3-sec3.0-0.dtsi2 * PQ3 Sec/Crypto 3.0 device tree stub [ controller @ offset 0x30000 ]
H A Dpq3-sec2.1-0.dtsi2 * PQ3 Sec/Crypto 2.1 device tree stub [ controller @ offset 0x30000 ]
H A Dpq3-sec3.1-0.dtsi2 * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ]
H A Dqoriq-sec6.0-0.dtsi2 * QorIQ Sec/Crypto 6.0 device tree stub
H A Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]

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