| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 84 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
121 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
443 case ISD::CopyFromReg: in SUSchedulingCost()
548 case ISD::CopyFromReg: in initNumRegDefsLeft()
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| H A D | StatepointLowering.cpp | 348 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
1198 SDValue CopyFromReg = getCopyFromRegs(SI, RetTy); in visitGCResult() local
1200 assert(CopyFromReg.getNode()); in visitGCResult()
1201 setValue(&CI, CopyFromReg); in visitGCResult()
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| H A D | ScheduleDAGRRList.cpp | 324 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
713 case ISD::CopyFromReg: in EmitNode()
1276 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2281 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2381 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2452 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2469 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
3016 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
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| H A D | InstrEmitter.cpp | 350 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
1146 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1238 case ISD::CopyFromReg: { in EmitSpecialNode()
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| H A D | ScheduleDAGSDNodes.cpp | 126 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
554 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
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| H A D | ScheduleDAGFast.cpp | 420 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
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| H A D | SelectionDAGDumper.cpp | 178 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
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| H A D | SelectionDAGBuilder.cpp | 5712 case ISD::CopyFromReg: { in getUnderlyingArgRegs()
10081 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) in visitPatchpoint()
10706 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
11248 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { in LowerArguments()
11257 if (Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
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| H A D | SelectionDAGISel.cpp | 3075 case ISD::CopyFromReg: in SelectCodeCommon()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 248 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
298 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
301 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 208 CopyFromReg, enumerator
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| H A D | SelectionDAG.h | 800 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
810 return getNode(ISD::CopyFromReg, dl, VTs,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragments.td | 662 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
665 // CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit
670 N->getOpcode() != ISD::CopyFromReg &&
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| H A D | X86ISelLoweringCall.cpp | 2635 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
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| H A D | X86ISelDAGToDAG.cpp | 390 if (OtherOp->getOpcode() == ISD::CopyFromReg && in shouldAvoidImmediateInstFormsForSize()
2585 RHS.getNode()->getOpcode() == ISD::CopyFromReg || in matchAddressRecursively()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 389 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
395 N->getOpcode() != ISD::CopyFromReg;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 323 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
2400 T1.getOpcode() != ISD::CopyFromReg && in LowerSELECT()
2401 T2.getOpcode() != ISD::CopyFromReg) { in LowerSELECT()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 11766 case ISD::CopyFromReg: { in calculateByteProvider()
12071 for (auto VectorwiseOp : {ISD::STORE, ISD::CopyToReg, ISD::CopyFromReg}) in performOrCombine()
15611 assert(N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
15618 } while (N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
15626 case ISD::CopyFromReg: { in isSDNodeSourceOfDivergence()
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| H A D | AMDGPUISelDAGToDAG.cpp | 1512 if (Val.getOpcode() != ISD::CopyFromReg) in IsCopyFromSGPR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 811 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1465 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3660 if (Ptr.getOpcode() == ISD::CopyFromReg && in Select()
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| H A D | ARMISelLowering.cpp | 2957 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
15167 Copy->getOpcode() == ISD::CopyFromReg) { in PerformVMOVhrCombine()
15173 DCI.DAG.getNode(ISD::CopyFromReg, SDLoc(N), in PerformVMOVhrCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 944 Opc != ISD::CopyFromReg && Opc != ISD::AssertSext && in SelectArithExtendedRegister()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4681 return AddrOp.getOpcode() == ISD::CopyFromReg; in isOffsetMultipleOf()
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