Searched refs:Cond0 (Results 1 – 4 of 4) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 3202 static bool isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0, in isSafeToRemoveBitCeilSelect() argument
3256 if (MatchForward(Cond0)) { in isSafeToRemoveBitCeilSelect()
3258 } else if (match(Cond0, m_Add(m_Value(CommonAncestor), m_APInt(C)))) { in isSafeToRemoveBitCeilSelect()
3304 Value *Cond0, *Ctlz, *CtlzOp; in foldBitCeil() local
3305 if (!match(SI.getCondition(), m_ICmp(Pred, m_Value(Cond0), m_APInt(Cond1)))) in foldBitCeil()
3320 !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth, in foldBitCeil()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Coroutines/ |
| H A D | CoroSplit.cpp | 1382 ConstantInt *Cond0 = TryResolveConstant(CondCmp->getOperand(0)); in simplifyTerminatorLeadingToRet() local
1384 if (!Cond0 || !Cond1) in simplifyTerminatorLeadingToRet()
1391 CondCmp->getPredicate(), Cond0, Cond1, DL)); in simplifyTerminatorLeadingToRet()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 11477 SDValue Cond0 = N0.getOperand(0); in foldVSelectToSignBitSplatMask() local
11480 if (VT != Cond0.getValueType()) in foldVSelectToSignBitSplatMask()
11496 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
11504 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
11515 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
11570 SDValue Cond0 = N0->getOperand(0); in visitSELECT() local
11575 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, in visitSELECT()
11583 SDValue Cond0 = N0->getOperand(0); in visitSELECT() local
11636 SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1); in visitSELECT() local
11645 combineMinNumMaxNum(DL, VT, Cond0, Cond1, N1, N2, CC)) in visitSELECT()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 45128 SDValue Cond0 = Cond.getOperand(0); in combineSelect() local
45151 if (LHS == Cond0 && RHS == Cond1) { in combineSelect()
45155 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
45160 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
45178 Cond0 == InnerSetCC.getOperand(0) && in combineSelect()
45189 Cond = DAG.getSetCC(DL, CondVT, Cond0, Cond1, NewCC); in combineSelect()
46279 SDValue Cond0 = Cond.getOperand(0); in combineCMov() local
46280 if (Cond0.getOpcode() == ISD::TRUNCATE) in combineCMov()
46281 Cond0 = Cond0.getOperand(0); in combineCMov()
46283 if (Cond0 == TrueOp && Sub1C && Sub1C->getZExtValue() == 2) { in combineCMov()
|