| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 138 Register CmpReg = AndCC->getReg(); in optimizeVcndVcmpPair() local
140 if (CmpReg == Register(ExecReg)) { in optimizeVcndVcmpPair()
142 CmpReg = AndCC->getReg(); in optimizeVcndVcmpPair()
148 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS); in optimizeVcndVcmpPair()
232 LiveInterval *CmpLI = CmpReg.isVirtual() ? &LIS->getInterval(CmpReg) : nullptr; in optimizeVcndVcmpPair()
234 (CmpReg == Register(CondReg) && in optimizeVcndVcmpPair()
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| H A D | AMDGPURegisterBankInfo.cpp | 917 auto CmpReg = B.buildICmp(CmpInst::ICMP_EQ, S1, CurrentLaneParts[i], in executeInWaterfallLoop() local
919 MRI.setRegBank(CmpReg, AMDGPU::VCCRegBank); in executeInWaterfallLoop()
922 CondReg = CmpReg; in executeInWaterfallLoop()
924 CondReg = B.buildAnd(S1, CondReg, CmpReg).getReg(0); in executeInWaterfallLoop()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 404 MCPhysReg CmpReg = KnownReg.Reg; in optimizeBlock() local
405 if (any_of(MI->implicit_operands(), [CmpReg](MachineOperand &O) { in optimizeBlock()
407 O.getReg() != CmpReg; in optimizeBlock()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 491 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
494 CmpReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); in LowerFPToInt()
509 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
520 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg); in LowerFPToInt()
521 CmpReg = AndReg; in LowerFPToInt()
524 BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg); in LowerFPToInt()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2203 Register CmpReg = fastEmitInst_rri(CmpOpcode, VK1, CmpLHSReg, CmpRHSReg, in X86FastEmitSSESelect() local
2216 unsigned MovReg = fastEmitInst_rrrr(MovOpcode, VR128X, RHSReg, CmpReg, in X86FastEmitSSESelect()
2236 Register CmpReg = fastEmitInst_rri(CmpOpcode, RC, CmpLHSReg, CmpRHSReg, in X86FastEmitSSESelect() local
2239 CmpReg); in X86FastEmitSSESelect()
2258 Register CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpRHSReg, CC); in X86FastEmitSSESelect() local
2259 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg); in X86FastEmitSSESelect()
2260 Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, RHSReg); in X86FastEmitSSESelect()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1290 Register CmpReg = getRegForValue(BI->getCondition()); in SelectBranch() local
1291 if (CmpReg == 0) return false; in SelectBranch()
1301 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); in SelectBranch()
1304 .addReg(CmpReg) in SelectBranch()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12180 unsigned CmpReg = Incr2Reg; in EmitPartwordAtomicBinary() local
12190 CmpReg = incr; in EmitPartwordAtomicBinary()
12192 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ValueReg).addReg(CmpReg); in EmitPartwordAtomicBinary()
12832 Register CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass); in EmitInstrWithCustomInserter() local
12834 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg) in EmitInstrWithCustomInserter()
12839 .addReg(CmpReg) in EmitInstrWithCustomInserter()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 17121 Register CmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in emitFROUND() local
17123 BuildMI(MBB, DL, TII.get(CmpOpc), CmpReg).addReg(FabsReg).addReg(MaxReg); in emitFROUND()
17129 .addReg(CmpReg) in emitFROUND()
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