Searched refs:CastVT (Results 1 – 5 of 5) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 2752 EVT CastVT = CastVal.getValueType(); in BitcastToInt_ATOMIC_SWAP() local
2755 = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, CastVT, in BitcastToInt_ATOMIC_SWAP()
2756 DAG.getVTList(CastVT, MVT::Other), in BitcastToInt_ATOMIC_SWAP()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4266 EVT CastVT = getPromotedVTForPredicate(InVT); in LowerVectorINT_TO_FP() local
4267 In = DAG.getNode(CastOpc, dl, CastVT, In); in LowerVectorINT_TO_FP()
4283 MVT CastVT = in LowerVectorINT_TO_FP() local
4287 In = DAG.getNode(Opc, dl, {CastVT, MVT::Other}, in LowerVectorINT_TO_FP()
4293 In = DAG.getNode(Opc, dl, CastVT, In); in LowerVectorINT_TO_FP()
4300 EVT CastVT = VT.changeVectorElementTypeToInteger(); in LowerVectorINT_TO_FP() local
4301 In = DAG.getNode(CastOpc, dl, CastVT, In); in LowerVectorINT_TO_FP()
11718 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, in tryFormConcatFromShuffle()
12018 MVT CastVT; in constructDup() local
12019 if (getScaledOffsetDup(V, Lane, CastVT)) { in constructDup()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 17734 Cond = DAG.getBitcast(CastVT, Cond); in LowerVSELECT()
17735 LHS = DAG.getBitcast(CastVT, LHS); in LowerVSELECT()
17736 RHS = DAG.getBitcast(CastVT, RHS); in LowerVSELECT()
21948 EVT CastVT = VecVT; in combineVectorSizedSetCCEquality() local
21955 CastVT = VecVT; in combineVectorSizedSetCCEquality()
21959 CastVT = OpSize == 512 ? VecVT in combineVectorSizedSetCCEquality()
21968 EVT TmpCastVT = CastVT; in combineVectorSizedSetCCEquality()
23197 Cmp = DAG.getBitcast(CastVT, Cmp); in LowerVSETCC()
24522 MVT CastVT = MVT::getVectorVT(StVT, 2); in LowerStore() local
50183 EVT CastVT = VT; in reduceMaskedLoadToScalarLoad() local
[all …]
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| H A D | X86InstrAVX512.td | 1701 X86VectorVTInfo CastVT> {
1705 (CastVT.VT _.RC:$src1))),
1707 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1713 (CastVT.VT _.RC:$src1))),
1715 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1720 (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))),
1722 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5770 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT); in lowerIntrinsicLoad() local
5771 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other); in lowerIntrinsicLoad()
5772 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT, in lowerIntrinsicLoad()
7317 static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT, in padEltsToUndef() argument
7332 return DAG.getBuildVector(CastVT, DL, Elts); in padEltsToUndef()
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