| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetFrameLoweringImpl.cpp | 100 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local 103 if (!CSRegs || CSRegs[0] == 0) in determineCalleeSaves() 126 for (unsigned i = 0; CSRegs[i]; ++i) { in determineCalleeSaves() 127 unsigned Reg = CSRegs[i]; in determineCalleeSaves()
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| H A D | RegUsageInfoCollector.cpp | 206 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF); in computeCalleeSavedRegs() local 207 for (unsigned i = 0; CSRegs[i]; ++i) { in computeCalleeSavedRegs() 208 MCPhysReg Reg = CSRegs[i]; in computeCalleeSavedRegs()
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| H A D | PrologEpilogInserter.cpp | 449 const MCPhysReg *CSRegs = F.getRegInfo().getCalleeSavedRegs(); in assignCalleeSavedSpillSlots() local 452 for (unsigned i = 0; CSRegs[i]; ++i) in assignCalleeSavedSpillSlots() 453 CSMask.set(CSRegs[i]); in assignCalleeSavedSpillSlots() 456 for (unsigned i = 0; CSRegs[i]; ++i) { in assignCalleeSavedSpillSlots() 457 unsigned Reg = CSRegs[i]; in assignCalleeSavedSpillSlots() 1339 for (const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF); in insertZeroCallUsedRegs() local 1340 MCPhysReg CSReg = *CSRegs; ++CSRegs) in insertZeroCallUsedRegs()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNNSAReassign.cpp | 81 const MCPhysReg *CSRegs; member in __anon8d12989f0111::GCNNSAReassign 133 for (unsigned I = 0; CSRegs[I]; ++I) in canAssign() 134 if (TRI->isSubRegisterEq(Reg, CSRegs[I]) && in canAssign() 135 !LRM->isPhysRegUsed(CSRegs[I])) in canAssign() 252 CSRegs = MRI->getCalleeSavedRegs(); in runOnMachineFunction()
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| H A D | SILowerSGPRSpills.cpp | 229 const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs(); in spillCalleeSavedRegs() local 231 for (unsigned I = 0; CSRegs[I]; ++I) { in spillCalleeSavedRegs() 232 MCRegister Reg = CSRegs[I]; in spillCalleeSavedRegs()
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| H A D | SIMachineFunctionInfo.cpp | 296 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); in splitWWMSpillRegisters() local 298 if (isCalleeSavedReg(CSRegs, Reg.first)) in splitWWMSpillRegisters() 305 bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs, in isCalleeSavedReg() argument 307 for (unsigned I = 0; CSRegs[I]; ++I) { in isCalleeSavedReg() 308 if (CSRegs[I] == Reg) in isCalleeSavedReg()
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| H A D | SIFrameLowering.cpp | 53 const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs(); in findScratchNonCalleeSaveRegister() local 54 for (unsigned i = 0; CSRegs[i]; ++i) in findScratchNonCalleeSaveRegister() 55 LiveUnits.addReg(CSRegs[i]); in findScratchNonCalleeSaveRegister() 1501 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); in determinePrologEpilogSGPRSaves() local 1502 for (unsigned I = 0; CSRegs[I]; ++I) in determinePrologEpilogSGPRSaves() 1503 LiveUnits.addReg(CSRegs[I]); in determinePrologEpilogSGPRSaves()
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| H A D | SIMachineFunctionInfo.h | 563 bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 120 const MCPhysReg *CSRegs) { in isCalleeSavedRegister() argument 121 for (unsigned i = 0; CSRegs[i]; ++i) in isCalleeSavedRegister() 122 if (Reg == CSRegs[i]) in isCalleeSavedRegister()
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| H A D | Thumb1FrameLowering.cpp | 693 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF); in emitPopSpecialFixUp() local 694 for (unsigned i = 0; CSRegs[i]; ++i) in emitPopSpecialFixUp() 695 UsedRegs.addReg(CSRegs[i]); in emitPopSpecialFixUp()
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| H A D | ARMFrameLowering.cpp | 2341 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); in determineCalleeSaves() local 2342 for (unsigned i = 0; CSRegs[i]; ++i) { in determineCalleeSaves() 2343 unsigned Reg = CSRegs[i]; in determineCalleeSaves()
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| H A D | ARMBaseInstrInfo.cpp | 2574 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); in tryFoldSPUpdateIntoPushPop() local 2596 if (isCalleeSavedRegister(CurReg, CSRegs) || in tryFoldSPUpdateIntoPushPop()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 380 static const MCPhysReg CSRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3, in determineCalleeSaves() local 383 for (unsigned i = 0; CSRegs[i]; ++i) in determineCalleeSaves() 384 SavedRegs.set(CSRegs[i]); in determineCalleeSaves()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 337 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); in homogeneousPrologEpilog() local 339 for (unsigned I = 0; CSRegs[I]; ++I) { in homogeneousPrologEpilog() 340 Register Reg = CSRegs[I]; in homogeneousPrologEpilog() 342 assert(CSRegs[I + 1] == AArch64::FP); in homogeneousPrologEpilog() 1000 const MCPhysReg *CSRegs = MF->getRegInfo().getCalleeSavedRegs(); in getLiveRegsForEntryMBB() local 1001 for (unsigned i = 0; CSRegs[i]; ++i) in getLiveRegsForEntryMBB() 1002 LiveRegs.addReg(CSRegs[i]); in getLiveRegsForEntryMBB() 3252 for (unsigned i = 0; CSRegs[i]; ++i) { in determineCalleeSaves() 3253 const unsigned Reg = CSRegs[i]; in determineCalleeSaves() 3267 PairedReg = CSRegs[i % 2 == 0 ? i - 1 : i + 1]; in determineCalleeSaves() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 485 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); in findScratchRegister() local 495 for (int i = 0; CSRegs[i]; ++i) in findScratchRegister() 496 BV.reset(CSRegs[i]); in findScratchRegister() 2329 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); in assignCalleeSavedSpillSlots() local 2357 for (unsigned i = 0; CSRegs[i]; ++i) in assignCalleeSavedSpillSlots() 2358 BVCalleeSaved.set(CSRegs[i]); in assignCalleeSavedSpillSlots()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.cpp | 281 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); in determineCalleeSaves() local 282 for (unsigned I = 0; CSRegs[I]; ++I) { in determineCalleeSaves() 283 unsigned Reg = CSRegs[I]; in determineCalleeSaves()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 998 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */ in determineCalleeSaves() local 1005 for (auto Reg : CSRegs) in determineCalleeSaves()
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