| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 322 CSINC, // Conditional select increment. enumerator
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| H A D | ARMISelLowering.cpp | 1894 MAKE_CASE(ARMISD::CSINC) in getTargetNodeName()
5459 Opcode = ARMISD::CSINC; in LowerSELECT_CC()
5461 Opcode = ARMISD::CSINC; in LowerSELECT_CC()
5470 if (Opcode != ARMISD::CSINC && in LowerSELECT_CC()
14043 SDValue CSINC = N->getOperand(1); in PerformSubCSINCCombine() local
14044 if (CSINC.getOpcode() != ARMISD::CSINC || !CSINC.hasOneUse()) in PerformSubCSINCCombine()
14054 CSINC.getOperand(1), CSINC.getOperand(2), in PerformSubCSINCCombine()
14055 CSINC.getOperand(3)); in PerformSubCSINCCombine()
18924 case ARMISD::CSINC: in PerformDAGCombine()
20147 case ARMISD::CSINC: in computeKnownBitsForTargetNode()
[all …]
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| H A D | ARMScheduleM85.td | 556 (instregex "t2(CSEL|CSINC|CSINV|CSNEG)")>;
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| H A D | ARMInstrInfo.td | 120 def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedThunderX2T99.td | 435 "CSINC(W|X)r", "CSINV(W|X)r",
457 "CSINC(W|X)r", "CSINV(W|X)r",
476 "CSINC(W|X)r", "CSINV(W|X)r",
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| H A D | AArch64SchedThunderX3T110.td | 695 "CSINC(W|X)r", "CSINV(W|X)r",
717 "CSINC(W|X)r", "CSINV(W|X)r",
736 "CSINC(W|X)r", "CSINV(W|X)r",
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| H A D | AArch64ISelLowering.h | 85 CSINC, // Conditional select increment. enumerator
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| H A D | AArch64SchedA64FX.td | 611 "CSINC(W|X)r", "CSINV(W|X)r",
631 "CSINC(W|X)r", "CSINV(W|X)r",
648 "CSINC(W|X)r", "CSINV(W|X)r",
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| H A D | AArch64SchedCyclone.td | 149 // CSEL,CSINC,CSINV,CSNEG
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| H A D | AArch64SchedTSV110.td | 404 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| H A D | AArch64SchedAmpere1.td | 952 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
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| H A D | AArch64SchedAmpere1B.td | 934 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
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| H A D | AArch64SchedFalkorDetails.td | 894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| H A D | AArch64SchedKryoDetails.td | 549 (instregex "(CSINC|CSNEG)(W|X)r")>;
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| H A D | AArch64ISelLowering.cpp | 2368 MAKE_CASE(AArch64ISD::CSINC) in getTargetNodeName()
9600 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC()
9612 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC()
10530 AArch64ISD::CSINC, DL, MVT::i32, DAG.getConstant(0, DL, MVT::i32), in getSETCC()
17838 return DAG.getNode(AArch64ISD::CSINC, DL, VT, DAG.getConstant(0, DL, VT), in performANDSETCCCombine()
18791 return DAG.getNode(AArch64ISD::CSINC, DL, VT, NewNode, RHS, CCVal, Cmp); in performAddCSelIntoCSinc()
18975 return DAG.getNode(AArch64ISD::CSINC, DL, VT, LHS, LHS, CC, Cond); in foldADCToCINC()
24150 AArch64ISD::CSINC, DL, MVT::i32, DAG.getConstant(0, DL, MVT::i32), in PerformDAGCombine()
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| H A D | AArch64InstrInfo.td | 665 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
2676 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 4714 auto CSINC = MIRBuilder.buildInstr(Opc, {Dst}, {Src1, Src2}).addImm(Pred); in emitCSINC() local
4715 constrainSelectedInstRegOperands(*CSINC, TII, TRI, RBI); in emitCSINC()
4716 return &*CSINC; in emitCSINC()
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