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Searched refs:CONCAT_VECTORS (Results 1 – 25 of 26) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp696 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
1431 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
1434 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1759 ISD::CONCAT_VECTORS, dl, OtherVT, in SplitVecRes_OverflowOp()
2596 ISD::CONCAT_VECTORS, DL, in SplitVecRes_VECTOR_SHUFFLE()
3251 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
3989 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
4463 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, in CollectOpsToWiden()
5593 else if (N.getOpcode() == ISD::CONCAT_VECTORS) { in isSETCCorConvertedSETCC()
7159 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, in GenWidenVectorLoads()
[all …]
H A DDAGCombiner.cpp11712 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
11713 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
11753 ISD::CONCAT_VECTORS, DL, VT, in ConvertSelectToConcatVector()
12421 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
12422 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
23545 if (Op.getOpcode() != ISD::CONCAT_VECTORS) in combineConcatVectorOfConcatVectors()
24486 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
25541 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
25544 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
25627 if (N1.getOpcode() == ISD::CONCAT_VECTORS) in visitVECTOR_SHUFFLE()
[all …]
H A DSelectionDAGDumper.cpp303 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
H A DSelectionDAG.cpp3174 case ISD::CONCAT_VECTORS: { in computeKnownBits()
4727 case ISD::CONCAT_VECTORS: { in ComputeNumSignBits()
5016 case ISD::CONCAT_VECTORS: in canCreateUndefOrPoison()
5643 case ISD::CONCAT_VECTORS: in getNode()
6059 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::CONCAT_VECTORS) in FoldConstantArithmetic()
6597 case ISD::CONCAT_VECTORS: { in getNode()
6845 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
6963 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
7103 case ISD::CONCAT_VECTORS: { in getNode()
9736 case ISD::CONCAT_VECTORS: in getNode()
H A DLegalizeDAG.cpp1498 Node->getOpcode() == ISD::CONCAT_VECTORS) && in ExpandVectorBuildThroughStack()
3394 case ISD::CONCAT_VECTORS: in ExpandNode()
5427 DAG.getNode(MidVT == NewEltVT ? ISD::BUILD_VECTOR : ISD::CONCAT_VECTORS, in PromoteNode()
5550 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
H A DSelectionDAGBuilder.cpp402 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
3886 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); in visitShuffleVector()
3904 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); in visitShuffleVector()
3905 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); in visitShuffleVector()
5726 case ISD::CONCAT_VECTORS: in getUnderlyingArgRegs()
11958 SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVec0, InVec1); in visitVectorInterleave()
11966 Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Res.getValue(0), in visitVectorInterleave()
H A DLegalizeIntegerTypes.cpp139 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
1530 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
1784 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
5782 DAG.getNode(ISD::CONCAT_VECTORS, dl, in PromoteIntRes_CONCAT_VECTORS()
H A DTargetLowering.cpp1304 case ISD::CONCAT_VECTORS: { in SimplifyDemandedBits()
3220 case ISD::CONCAT_VECTORS: { in SimplifyDemandedVectorElts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp177 setOperationAction(ISD::CONCAT_VECTORS, P, Custom); in initializeHVXLowering()
231 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
275 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
388 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom); in initializeHVXLowering()
550 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
1623 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); in LowerHvxBuildVector()
1732 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1734 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
2996 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1), in SplitHvxMemOp()
3027 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, MLoad0, MLoad1), in SplitHvxMemOp()
[all …]
H A DHexagonISelLowering.cpp1645 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1695 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
2178 return Op.getOpcode() == ISD::CONCAT_VECTORS || in isTargetCanonicalConstantNode()
2440 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, in LowerVECTOR_SHIFT()
2901 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats); in appendUndef()
3344 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp1910 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1}); in scalarizeShuffle()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h543 CONCAT_VECTORS, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2436 ISD::CONCAT_VECTORS, in X86TargetLowering()
3926 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in collectConcatOps()
4040 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in splitVectorOp()
6306 if (Opcode == ISD::CONCAT_VECTORS) { in getShuffleScalarElt()
8440 ISD::CONCAT_VECTORS, DL, VT, in createVariablePermute()
12390 case ISD::CONCAT_VECTORS: { in lowerShuffleAsBroadcast()
40788 if (N0.getOpcode() != ISD::CONCAT_VECTORS || in combineShuffleOfConcatUndef()
48437 if (Src.getOpcode() != ISD::CONCAT_VECTORS) in combineScalarAndWithMaskSetcc()
49452 ISD::CONCAT_VECTORS, dl, VT, in combineOr()
49460 ISD::CONCAT_VECTORS, dl, VT, in combineOr()
[all …]
H A DX86ISelLoweringCall.cpp1051 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v64i1, Lo, Hi); in getv64i1Argument()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp253 case ISD::CONCAT_VECTORS: in getIdiomaticVectorType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1385 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1710 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
1865 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in addTypeForFixedLengthSVE()
6208 case ISD::CONCAT_VECTORS: in LowerOperation()
12027 } else if (V.getOpcode() == ISD::CONCAT_VECTORS) { in constructDup()
13322 SDValue CONCAT_VECTORS = in LowerBUILD_VECTOR() local
13324 return CONCAT_VECTORS; in LowerBUILD_VECTOR()
18213 DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in performConcatVectorsCombine()
19299 BV.getOpcode() == ISD::CONCAT_VECTORS) { in isLoadOrMultipleLoads()
23901 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp181 ISD::FP_ROUND, ISD::CONCAT_VECTORS}); in WebAssemblyTargetLowering()
2586 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in performVectorTruncZeroCombine()
2755 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedVT, Lo, Hi); in truncateVectorWithNARROW()
2883 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp724 setOperationAction({ISD::TRUNCATE, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
1276 setOperationAction({ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
1403 ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
4779 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in lowerVECTOR_SHUFFLE()
6441 case ISD::CONCAT_VECTORS: { in LowerOperation()
9710 SDValue Even = DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, in lowerVECTOR_DEINTERLEAVE()
9788 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, in lowerVECTOR_INTERLEAVE()
9790 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, in lowerVECTOR_INTERLEAVE()
14787 if (InVec.getOpcode() != ISD::CONCAT_VECTORS) in performINSERT_VECTOR_ELTCombine()
14810 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps); in performINSERT_VECTOR_ELTCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp186 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
445 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in addMVEVectorTypes()
8129 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); in LowerBUILD_VECTOR()
9393 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, Ext, Ext1); in LowerVectorExtend()
9781 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
9818 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
15674 return DCI.DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, Lo, Hi); in PerformInsertSubvectorCombine()
15719 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
15720 Op1.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
15736 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, in PerformVECTOR_SHUFFLECombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp830 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp338 case ISD::CONCAT_VECTORS: in SITargetLowering()
635 case ISD::CONCAT_VECTORS: in SITargetLowering()
5460 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
5486 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
5518 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitTernaryVectorOp()
7005 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
7918 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); in lowerSBuffer()
H A DAMDGPUISelLowering.cpp383 setOperationAction(ISD::CONCAT_VECTORS, in AMDGPUTargetLowering()
1336 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1770 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td749 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2696 case ISD::CONCAT_VECTORS: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8581 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops); in widenVec()

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