| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.h | 43 CMOV, enumerator
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| H A D | ARCISelLowering.cpp | 185 case ARCISD::CMOV: in getTargetNodeName()
213 return DAG.getNode(ARCISD::CMOV, dl, TVal.getValueType(), TVal, FVal, in LowerSELECT_CC()
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| H A D | ARCInstrInfo.td | 55 def ARCcmov : SDNode<"ARCISD::CMOV", SDT_ARCcmov, [SDNPInGlue]>;
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| /freebsd-14.2/sys/contrib/xen/arch-x86/ |
| H A D | cpufeatureset.h | 109 XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present)…
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrCMovSetCC.td | 15 // CMOV instructions.
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| H A D | X86ISelLowering.h | 117 CMOV, enumerator
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| H A D | X86InstrFragments.td | 141 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
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| H A D | X86ISelLowering.cpp | 27860 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops); in LowerCTLZ()
27894 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops); in LowerCTTZ()
27994 return DAG.getNode(X86ISD::CMOV, DL, VT, Ops); in LowerABS()
33159 NODE_NAME_CASE(CMOV) in getTargetNodeName()
36703 case X86ISD::CMOV: { in computeKnownBitsForTargetNode()
36990 case X86ISD::CMOV: { in ComputeNumSignBitsForTargetNode()
45545 case X86ISD::CMOV: { in checkBoolTestSetCCCombine()
46329 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), Ops); in combineCMov() local
46330 return CMOV; in combineCMov()
53756 case X86ISD::CMOV: in needCarryOrOverflowFlag()
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| H A D | X86InstrAsmAlias.td | 629 // CMOV SETCC Aliases
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| H A D | X86InstrCompiler.td | 539 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
542 def CMOV#NAME : I<0, Pseudo,
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| H A D | X86ISelDAGToDAG.cpp | 3350 case X86ISD::CMOV: CCOpNo = 2; break; in hasNoCarryFlagUses()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.h | 63 CMOV, enumerator
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| H A D | M68kInstrCompiler.td | 53 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
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| H A D | M68kISelLowering.cpp | 2403 SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond); in LowerSELECT()
2423 return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops); in LowerSELECT()
3681 case M68kISD::CMOV: in getTargetNodeName()
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| H A D | M68kInstrInfo.td | 133 def MxCmov : SDNode<"M68kISD::CMOV", MxSDT_Cmov>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.h | 31 CMOV, // Select between two values using the result of comparison. enumerator
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| H A D | VEInstrInfo.td | 460 def cmov : SDNode<"VEISD::CMOV", SDT_Cmov>;
723 // Multiclass for CMOV instructions.
1313 // Section 8.5.11 - CMOV (Conditional Move)
2029 // CMOV %res, (63)0, %tmp ; set 1 if %tmp is true
2053 // Generic CMOV pattern matches
2054 // CMOV accepts i64 $t, $f, and result. So, we extend it to support
2057 // CMOV for i32
2077 // CMOV for f32
2098 // CMOV for f64
2111 // CMOV for f128
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| H A D | VEISelLowering.cpp | 940 TARGET_NODE_CASE(CMOV) in getTargetNodeName()
2827 return DAG.getNode(VEISD::CMOV, DL, VT, Ops); in combineSelect()
2895 return DAG.getNode(VEISD::CMOV, DL, VT, Ops); in combineSelectCC()
2934 case VEISD::CMOV: in isI32Insn()
2977 User->getOpcode() == ISD::SELECT || User->getOpcode() == VEISD::CMOV) in isI32InsnAllUses()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/TargetParser/ |
| H A D | X86TargetParser.def | 138 X86_FEATURE_COMPAT(CMOV, "cmov", 0)
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSchedSiFiveP400.td | 63 // CMOV
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 97 CMOV, // ARM conditional move instructions. enumerator
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| H A D | ARMISelLowering.cpp | 1719 MAKE_CASE(ARMISD::CMOV) in getTargetNodeName()
5144 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { in LowerSELECT()
6378 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, in LowerShiftLeftParts()
18079 SDValue Op0 = CMOV->getOperand(0); in PerformCMOVToBFICombine()
18080 SDValue Op1 = CMOV->getOperand(1); in PerformCMOVToBFICombine()
18081 auto CC = CMOV->getConstantOperandAPInt(2).getLimitedValue(); in PerformCMOVToBFICombine()
18082 SDValue CmpZ = CMOV->getOperand(4); in PerformCMOVToBFICombine()
18343 LHS->getOperand(0)->getOpcode() == ARMISD::CMOV && in PerformBRCONDCombine()
18490 Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, FalseVal, in PerformCMOVCombine()
18918 case ARMISD::CMOV: in PerformDAGCombine()
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| H A D | ARMISelDAGToDAG.cpp | 4236 case ARMISD::CMOV: { in Select()
4259 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops); in Select()
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| H A D | ARMInstrFormats.td | 166 // Selectable predicate operand for CMOV instructions. We can't use a normal
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| H A D | ARMInstrInfo.td | 161 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
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