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Searched refs:CDIV (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/sys/arm64/rockchip/clk/
H A Drk3568_cru.c329 CDIV(0, "atclk_core_div", "armclk", 0, 3, 0, 5),
331 CDIV(0, "gicclk_core_div", "armclk", 0, 3, 8, 5),
335 CDIV(0, "pclk_core_pre_div", "armclk", 0, 4, 0, 5),
363 CDIV(0, "hclk_npu_pre_div", "clk_npu", 0, 8, 0, 4),
375 CDIV(0, "clk_msch_div", "clk_ddr1x", 0, 10, 0, 2),
499 CDIV(0, "pclk_php_div", "aclk_php", 0, 30, 4, 4),
525 CDIV(0, "pclk_usb_div", "aclk_usb", 0, 32, 4, 4),
550 CDIV(0, "hclk_vi_div", "aclk_vi", 0, 34, 4, 4),
551 CDIV(0, "pclk_vi_div", "aclk_vi", 0, 34, 8, 4),
567 CDIV(0, "hclk_vo_div", "aclk_vo", 0, 37, 8, 4),
[all …]
H A Drk3399_cru.c793 CDIV(0, "aclkm_core_l_c", "armclkl", 0,
800 CDIV(0, "atclk_core_l_c", "armclkl", 0,
804 CDIV(0, "aclkm_core_b_c", "armclkb", 0,
814 CDIV(0, "atclk_core_b_c", "armclkb", 0,
952 CDIV(0, "clk_saradc_c", "xin24m", 0,
1053 CDIV(0, "pclk_hdcp_c", "aclk_hdcp", 0,
1055 CDIV(0, "hclk_hdcp_c", "aclk_hdcp", 0,
1057 CDIV(0, "pclk_vio_c", "aclk_vio", 0,
1105 CDIV(0, "hclk_isp0_c", "aclk_isp0", 0,
1111 CDIV(0, "hclk_isp1_c", "aclk_isp1", 0,
[all …]
H A Drk3288_cru.c608 CDIV(0, "sclk_tsadc_s", "xin32k", 0,
614 CDIV(0, "uart4_src_s", "uart_src", 0,
759 CDIV(0, "hclk_vio", "aclk_vio0", 0,
789 CDIV(0, "pclk_pd_alive", "gpll", 0,
791 CDIV(0, "pclk_pd_pmu_s", "gpll", 0,
807 CDIV(0, "armcore3_s", "armclk", 0,
809 CDIV(0, "armcore2_s", "armclk", 0,
811 CDIV(0, "armcore1_s", "armclk", 0,
813 CDIV(0, "armcore0_s", "armclk", 0,
819 CDIV(0, "atclk_s", "armclk", 0,
[all …]
H A Drk3568_pmucru.c110 CDIV(0, "xin_osc0_div_div", "xin24m", 0, 0, 0, 5),
117 CDIV(0, "pclk_pdpmu_pre", "clk_pdpmu", 0, 2, 0, 5),
121 CDIV(0, "clk_i2c0_div", "clk_pdpmu", 0, 3, 0, 7),
124 CDIV(0, "sclk_uart0_div_div", "sclk_uart0_div_sel", 0, 4, 0, 7),
132 CDIV(0, "clk_pwm0_div", "clk_pwm0_sel", 0, 6, 0, 7),
137 CDIV(0, "clk_ref24m_div", "clk_pdpmu", 0, 7, 0, 6),
145 CDIV(0, "clk_wifi_div_div", "clk_pdpmu", 0, 8, 8, 6),
149 CDIV(0, "clk_pciephy0_div_div", "ppll_ph0", 0, 9, 0, 3),
152 CDIV(0, "clk_pciephy1_div_div", "ppll_ph0", 0, 9, 4, 3),
155 CDIV(0, "clk_pciephy2_div_div", "ppll_ph0", 0, 9, 8, 3),
H A Drk3328_cru.c865 CDIV(0, "hclk_bus_pre_c", "aclk_bus_pre", 0, 1, 8, 2),
866 CDIV(0, "pclk_bus_pre_c", "aclk_bus_pre", 0, 1, 12, 2),
908 CDIV(0, "clk_spdif_div_c", "clk_spdif_pll", 0, 12, 0, 7),
916 CDIV(0, "clk_uart0_div_c", "clk_uart0_pll", 0, 14, 0, 7),
924 CDIV(0, "clk_uart1_div_c", "clk_uart1_pll", 0, 16, 0, 7),
932 CDIV(0, "clk_uart2_div_c", "clk_uart2_pll", 0, 18, 0, 7),
945 CDIV(0, "clk_tsadc_c", "xin24m", 0, 22, 0, 10),
948 CDIV(0, "clk_saradc_c", "xin24m", 0, 23, 0, 10),
956 CDIV(0, "pclk_gmac_c", "pclk_gmac", 0, 25, 8, 3),
970 CDIV(0, "pclk_peri_c", "aclk_peri_pre", 0, 29, 0, 2),
[all …]
H A Drk3399_pmucru.c787 CDIV(PCLK_PMU_SRC, "pclk_pmu_src", "ppll", 0, 0, 0, 5),
800 CDIV(0, "clk_i2c0_div", "ppll", 0, 2, 0, 7),
802 CDIV(0, "clk_i2c8_div", "ppll", 0, 2, 8, 7),
806 CDIV(0, "clk_i2c4_div", "ppll", 0, 3, 0, 7),
H A Drk_cru.h158 #define CDIV(_id, _name, _pname, _f, _o, _ds, _dw) \ macro