Home
last modified time | relevance | path

Searched refs:CCOp (Results 1 – 14 of 14) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td232 def CCOp : Operand<i32>;
935 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
986 (ins bprtarget:$imm19, CCOp:$cond),
990 (ins bprtarget:$imm19, CCOp:$cond),
1525 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1531 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1540 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1554 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1573 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1578 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
[all …]
H A DSparcInstr64Bit.td313 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
318 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
326 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
331 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
337 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.td405 def CCOpAsmOperand : AsmOperandClass { let Name = "CCOp"; }
406 def CCOp : Operand<i32>, ImmLeaf<i32, [{
733 (i32 CCOp:$cfw)))]>;
736 (ins CCOp:$cfw, immOp:$sy, I64:$sz, I64:$sd),
739 (i32 CCOp:$cfw)))]>;
742 (ins CCOp:$cfw, RC:$sy, mimm:$sz, I64:$sd),
745 (i32 CCOp:$cfw)))]>;
748 (ins CCOp:$cfw, immOp:$sy, mimm:$sz, I64:$sd),
751 (i32 CCOp:$cfw)))]>;
850 defm r : BCtgm<opcStr, "$sy, ", opc, (ins CCOp:$cond, RC:$sy)>;
[all …]
H A DVEInstrVec.td60 (ins CCOp:$cf, V64:$vz, I32:$vl),
63 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
66 (ins CCOp:$cf, V64:$vz, I32:$vl),
69 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
766 defm v : RVMKlm<opcStr#"$vy", ", $vz", opc, RCM, (ins CCOp:$vy, RC:$vz)>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td231 def CCOp : Operand<i32> {
685 def BRCC : InstBR<(outs), (ins BrTarget:$addr, CCOp:$DDDI),
768 def SCC : InstSCC<(outs GPR:$Rs1), (ins CCOp:$DDDI),
776 (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
788 def BRIND_CC : InstRR<0b101, (outs), (ins GPR:$Rs1, CCOp:$DDDI),
796 def BRIND_CCA : InstRR<0b101, (outs), (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
808 def BRR : InstBRR<(outs), (ins i16imm:$imm16, CCOp:$DDDI),
H A DLanaiISelLowering.cpp1425 SDValue CCOp; in combineSelectAndUse() local
1427 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
1439 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal); in combineSelectAndUse()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.td21 def CCOp : PredicateOperand<i32, (ops i32imm), (ops)>;
398 (outs GPR32:$B), (ins GPR32:$C, GPR32:$B2, CCOp:$cc),
403 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
407 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp190 struct CCOp { struct in __anonb0359a6c0211::VEOperand
208 struct CCOp CC;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp356 bool Negate, Register CCOp,
4930 Register Val, AArch64CC::CondCode &OutCC, bool Negate, Register CCOp, in emitConjunctionRec() argument
4952 if (!CCOp) in emitConjunctionRec()
4957 CCOp = ExtraCmp->getOperand(0).getReg(); in emitConjunctionRec()
4963 if (!CCOp) { in emitConjunctionRec()
5033 emitConjunctionRec(RHS, RHSCC, NegateR, CCOp, Predicate, MIB); in emitConjunctionRec()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2184 const MachineOperand &CCOp = I.getOperand(1); in selectG_SELECT() local
2185 Register CCReg = CCOp.getReg(); in selectG_SELECT()
2196 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4096 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get(); in ExpandNode() local
4098 if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) { in ExpandNode()
4116 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, Tmp1.getValueType()); in ExpandNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3274 ISD::CondCode CC, SDValue CCOp, in emitConditionalComparison() argument
3303 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp); in emitConditionalComparison()
3383 AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, in emitConjunctionRec() argument
3406 if (!CCOp.getNode()) in emitConjunctionRec()
3409 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, in emitConjunctionRec()
3411 CCOp = ExtraCmp; in emitConjunctionRec()
3417 if (!CCOp) in emitConjunctionRec()
3420 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL, in emitConjunctionRec()
3481 SDValue CmpR = emitConjunctionRec(DAG, RHS, RHSCC, NegateR, CCOp, Predicate); in emitConjunctionRec()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp789 struct CCOp { struct in __anon2f82d7160111::ARMOperand
912 struct CCOp CC;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12580 SDValue CCOp; in combineSelectAndUse() local
12582 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
12595 CCOp, TrueVal, FalseVal); in combineSelectAndUse()