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Searched refs:BitVector (Results 1 – 25 of 287) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ADT/
H A DBitVector.h82 class BitVector {
351 BitVector &set() { in set()
431 BitVector &flip() { in flip()
509 BitVector &operator&=(const BitVector &RHS) {
526 BitVector &reset(const BitVector &RHS) { in reset()
552 static BitVector &apply(F &&f, BitVector &Out, BitVector const &Arg, in apply()
565 BitVector &operator|=(const BitVector &RHS) {
573 BitVector &operator^=(const BitVector &RHS) {
835 inline BitVector::size_type capacity_in_bytes(const BitVector &X) { in capacity_in_bytes()
842 BitVector V;
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H A DSmallBitVector.h95 BitVector *getPointer() const { in getPointer()
97 return reinterpret_cast<BitVector *>(X); in getPointer()
106 void switchToLarge(BitVector *BV) { in switchToLarge()
152 switchToLarge(new BitVector(s, t));
160 switchToLarge(new BitVector(*RHS.getPointer())); in SmallBitVector()
340 BitVector *BV = new BitVector(N, t);
353 BitVector *BV = new BitVector(SmallSize); in reserve()
620 switchToLarge(new BitVector(*RHS.getPointer()));
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DStackLifetime.h46 BitVector Begin;
49 BitVector End;
52 BitVector LiveIn;
55 BitVector LiveOut;
64 BitVector Bits;
113 BitVector InterestingAllocas;
169 static inline raw_ostream &operator<<(raw_ostream &OS, const BitVector &V) {
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses;
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
127 void getSubRegs(unsigned Reg, BitVector &SRs) const;
128 void expandReg(unsigned Reg, BitVector &Set) const;
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
130 BitVector &Uses) const;
146 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs()
151 void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const { in expandReg()
159 BitVector &Uses) const { in getDefsUses()
173 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
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H A DHexagonFrameLowering.h23 class BitVector; variable
79 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
128 BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h63 BitVector Seen;
76 using EntryInfoMap = DenseMap<LiveRange *, std::pair<BitVector, BitVector>>;
130 MachineBasicBlock &MBB, BitVector &DefOnEntry,
131 BitVector &UndefOnEntry);
H A DLiveRegUnits.h32 BitVector Units;
144 void addUnits(const BitVector &RegUnits) { in addUnits()
148 void removeUnits(const BitVector &RegUnits) { in removeUnits()
152 const BitVector &getBitVector() const { in getBitVector()
H A DRDFRegisters.h162 const BitVector &getMaskUnits(RegisterId MaskId) const { in getMaskUnits()
168 const BitVector &getUnitAliases(uint32_t U) const { in getUnitAliases()
190 BitVector Units;
193 BitVector Regs;
217 return DenseMapInfo<BitVector>::isEqual(Units, A.Units);
236 size_t hash() const { return DenseMapInfo<BitVector>::getHashValue(Units); } in hash()
272 using unit_iterator = typename BitVector::const_set_bits_iterator;
284 BitVector Units;
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DSpillPlacement.h37 class BitVector; variable
51 BitVector *ActiveNodes = nullptr;
108 void prepare(BitVector &RegBundles);
H A DRegUsageInfoCollector.cpp60 static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
137 BitVector SavedRegs; in runOnMachineFunction()
140 const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask(); in runOnMachineFunction()
195 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) { in computeCalleeSavedRegs()
H A DStackColoring.cpp388 BitVector Begin;
391 BitVector End;
394 BitVector LiveIn;
397 BitVector LiveOut;
429 BitVector InterestingSlots;
433 BitVector ConservativeSlots;
456 void dumpBV(const char *tag, const BitVector &BV) const;
641 BitVector BetweenStartEnd; in collectMarkers()
692 BitVector &SeenStart = SeenStartMap[MBB]; in collectMarkers()
787 BitVector LocalLiveIn; in calculateLocalLiveness()
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H A DLiveRangeCalc.cpp123 MachineBasicBlock &MBB, BitVector &DefOnEntry, in isDefOnEntry()
124 BitVector &UndefOnEntry) { in isDefOnEntry()
304 std::make_pair(&LR, std::make_pair(BitVector(), BitVector()))); in findReachingDefs()
311 BitVector &DefOnEntry = Entry->second.first; in findReachingDefs()
312 BitVector &UndefOnEntry = Entry->second.second; in findReachingDefs()
441 BitVector DefBlocks(MF.getNumBlockIDs()); in isJointlyDominated()
H A DCFIInstrInserter.cpp79 BitVector IncomingCSRSaved;
81 BitVector OutgoingCSRSaved;
185 BitVector CSRSaved(NumRegs), CSRRestored(NumRegs); in calculateOutgoingCFAInfo()
273 BitVector::apply([](auto x, auto y, auto z) { return (x | y) & ~z; }, in calculateOutgoingCFAInfo()
303 BitVector SetDifference; in insertCFIInstrs()
355 BitVector::apply([](auto x, auto y) { return x & ~y; }, SetDifference, in insertCFIInstrs()
365 BitVector::apply([](auto x, auto y) { return x & ~y; }, SetDifference, in insertCFIInstrs()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/
H A DOMPContext.h148 BitVector RequiredTraits = BitVector(unsigned(TraitProperty::Last) + 1);
175 BitVector ActiveTraits = BitVector(unsigned(TraitProperty::Last) + 1);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.cpp24 BitVector SPIRVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs()
25 return BitVector(getNumRegs()); in getReservedRegs()
/freebsd-14.2/contrib/llvm-project/clang/lib/Analysis/
H A DIntervalPartition.cpp39 BuildResult<Node> buildInterval(llvm::BitVector &Partitioned, in buildInterval()
51 llvm::BitVector Workset(Partitioned.size(), false); in buildInterval()
108 llvm::BitVector &Partitioned, const Node *Header) { in fillIntervalNode()
155 llvm::BitVector Partitioned(NumBlockIDs, false); in partitionIntoIntervalsImpl()
200 llvm::BitVector Partitioned(Header->getParent()->getNumBlockIDs(), false); in buildInterval()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/
H A DCodeGenCoverage.h21 BitVector RuleCoverage;
24 using const_covered_iterator = BitVector::const_set_bits_iterator;
H A DProgram.h26 class BitVector; variable
140 BitVector *AffinityMask = nullptr ///< CPUs or processors the new
155 BitVector *AffinityMask = nullptr);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPostRABundler.cpp52 BitVector &UsedRegUnits) const;
92 BitVector &UsedRegUnits) const { in collectUsedRegUnits()
129 BitVector BundleUsedRegUnits(TRI->getNumRegUnits()); in runOnMachineFunction()
130 BitVector KillUsedRegUnits(TRI->getNumRegUnits()); in runOnMachineFunction()
H A DSIFrameLowering.h33 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
35 void determineCalleeSavesSGPR(MachineFunction &MF, BitVector &SavedRegs,
37 void determinePrologEpilogSGPRSaves(MachineFunction &MF, BitVector &SavedRegs,
H A DR600RegisterInfo.cpp36 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs()
37 BitVector Reserved(getNumRegs()); in getReservedRegs()
113 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { in reserveRegisterTuples()
H A DR600RegisterInfo.h29 BitVector getReservedRegs(const MachineFunction &MF) const override;
54 void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Support/
H A DProgram.cpp30 BitVector *AffinityMask);
38 BitVector *AffinityMask) { in ExecuteAndWait()
61 bool *ExecutionFailed, BitVector *AffinityMask) { in ExecuteNoWait()
/freebsd-14.2/contrib/llvm-project/clang/lib/Analysis/FlowSensitive/
H A DControlFlowContext.cpp48 static llvm::BitVector findReachableBlocks(const CFG &Cfg) { in findReachableBlocks()
49 llvm::BitVector BlockReachable(Cfg.getNumBlockIDs(), false); in findReachableBlocks()
114 llvm::BitVector BlockReachable = findReachableBlocks(*Cfg); in build()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Analysis/Analyses/
H A DReachableCode.h23 class BitVector; variable
59 llvm::BitVector &Reachable);

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