Searched refs:BaseRegOp (Results 1 – 3 of 3) sorted by relevance
764 const MachineOperand &BaseRegOp = in mergeNarrowZeroStores() local798 .add(BaseRegOp) in mergeNarrowZeroStores()982 const MachineOperand &BaseRegOp = in mergePairedInsns() local1069 MIB.addReg(BaseRegOp.getReg(), RegState::Define); in mergePairedInsns()1073 .add(BaseRegOp) in mergePairedInsns()
2822 const MachineOperand &BaseRegOp = MemI.getOperand(0); in canFoldIntoAddrMode() local2823 if (BaseRegOp.isReg() && BaseRegOp.getReg() == Reg) in canFoldIntoAddrMode()
3755 const MCOperand &BaseRegOp = Inst.getOperand(StartOp + 1); in expandMem16Inst() local3756 assert(BaseRegOp.isReg() && "expected register operand kind"); in expandMem16Inst()3762 unsigned BaseReg = BaseRegOp.getReg(); in expandMem16Inst()3882 const MCOperand &BaseRegOp = Inst.getOperand(StartOp + 1); in expandMem9Inst() local3883 assert(BaseRegOp.isReg() && "expected register operand kind"); in expandMem9Inst()3889 unsigned BaseReg = BaseRegOp.getReg(); in expandMem9Inst()