| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrArithmetic.td | 609 def 8rr_NF : BinOpRR_R<BaseOpc, mnemonic, Xi8>, NF;
611 def 32rr_NF : BinOpRR_R<BaseOpc, mnemonic, Xi32>, NF;
612 def 64rr_NF : BinOpRR_R<BaseOpc, mnemonic, Xi64>, NF;
731 def 8mr_NF : BinOpMR_M<BaseOpc, mnemonic, Xi8>, NF;
733 def 32mr_NF : BinOpMR_M<BaseOpc, mnemonic, Xi32>, NF;
734 def 64mr_NF : BinOpMR_M<BaseOpc, mnemonic, Xi64>, NF;
908 def 8mr : BinOpMRF_MF<BaseOpc, mnemonic, Xi8 , opnode>;
982 def 8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
986 def 64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
1014 def 8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
[all …]
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| H A D | X86FastISel.cpp | 2871 unsigned BaseOpc, CondCode; in fastLowerIntrinsicCall() local
2875 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2877 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2879 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2881 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2883 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2885 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2900 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && in fastLowerIntrinsicCall()
2904 bool IsDec = BaseOpc == ISD::SUB; in fastLowerIntrinsicCall()
2922 if (BaseOpc == X86ISD::UMUL && !ResultReg) { in fastLowerIntrinsicCall()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 703 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm in CreateLoadStoreMulti() local
715 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm in CreateLoadStoreMulti()
738 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
756 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
758 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
763 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
769 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 439 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
457 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
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| H A D | AMDGPUBaseInfo.cpp | 379 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMTBUFOpcode() argument
380 const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMTBUFOpcode()
409 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMUBUFOpcode() argument
410 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMUBUFOpcode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 957 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in ScalarizeVecOp_VECREDUCE_SEQ() local
960 return DAG.getNode(BaseOpc, SDLoc(N), N->getValueType(0), in ScalarizeVecOp_VECREDUCE_SEQ()
6796 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE() local
6797 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE()
6834 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE_SEQ() local
6835 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE_SEQ()
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| H A D | DAGCombiner.cpp | 942 auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), in match() local
944 if (BaseOpc != Opc) in match()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 3202 unsigned BaseOpc = BO.first.getOpcode(); in LowerUnalignedLoad() local
3203 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
3211 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 9120 unsigned BaseOpc; in lowerVectorMaskVecReduction() local
9134 BaseOpc = ISD::AND; in lowerVectorMaskVecReduction()
9142 BaseOpc = ISD::OR; in lowerVectorMaskVecReduction()
9151 BaseOpc = ISD::XOR; in lowerVectorMaskVecReduction()
9168 return DAG.getNode(BaseOpc, DL, Op.getValueType(), SetCC, Op.getOperand(0)); in lowerVectorMaskVecReduction()
9216 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode()); in lowerVECREDUCE() local
9224 Vec = DAG.getNode(BaseOpc, DL, VecEVT, Lo, Hi); in lowerVECREDUCE()
9244 SDValue StartV = DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags()); in lowerVECREDUCE()
9245 switch (BaseOpc) { in lowerVECREDUCE()
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