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Searched refs:BaseOp (Results 1 – 25 of 29) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp154 const MachineOperand *BaseOp; in runOnMachineFunction() local
157 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in runOnMachineFunction()
159 BaseOp->isReg()) { in runOnMachineFunction()
160 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction()
H A DAArch64InstrInfo.h166 const MachineOperand *&BaseOp,
H A DAArch64InstrInfo.cpp2681 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2683 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth()
2692 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
3469 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
3501 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
3505 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
3510 if (!BaseOp->isReg() && !BaseOp->isFI()) in getMemOperandWithOffsetWidth()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp109 static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, in getBaseOffset() argument
129 BaseOp = &MI.getOperand(1); in getBaseOffset()
141 BaseOp = &MI.getOperand(1); in getBaseOffset()
146 BaseOp = &MI.getOperand(2); in getBaseOffset()
160 BaseOp = &MI.getOperand(1); in getBaseOffset()
H A DARMLoadStoreOptimizer.cpp1624 Register Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble()
1659 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble()
1770 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1795 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1796 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
3018 MI->getOperand(BaseOp).setReg(NewBaseReg); in AdjustBaseAndOffset()
3158 int BaseOp = getBaseOperandIndex(Use); in DistributeIncrements() local
3159 if (BaseOp == -1) in DistributeIncrements()
3162 if (!Use.getOperand(BaseOp).isReg() || in DistributeIncrements()
3287 int BaseOp = getBaseOperandIndex(MI); in DistributeIncrements() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp754 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
785 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
788 if (!BaseOp->isReg()) in getMemOperandWithOffsetWidth()
810 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
812 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
814 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
H A DLanaiInstrInfo.h77 const MachineOperand *&BaseOp,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp430 MachineOperand BaseOp = MI->getOperand(getBaseOpPosition(MI)); in processAddUses() local
432 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) in processAddUses()
496 MachineOperand &BaseOp = UseMI->getOperand(getBaseOpPosition(UseMI)); in updateAddUses() local
498 BaseOp.setReg(NewReg); in updateAddUses()
499 BaseOp.setIsUndef(AddRegOp.isUndef()); in updateAddUses()
500 BaseOp.setImplicit(AddRegOp.isImplicit()); in updateAddUses()
H A DHexagonInstrInfo.cpp1173 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1179 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1188 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1196 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1201 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1217 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1234 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1239 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
3049 if (!BaseOp || !BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
3051 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp132 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1; in checkADDrr() local
169 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td644 field string BaseOp;
653 let BaseOp = name;
659 let BaseOp = name;
675 field string BaseOp;
683 let BaseOp = name;
689 let BaseOp = name;
H A DSIInstrInfo.cpp378 if (!BaseOp) { in getMemOperandsWithOffsetWidth()
383 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
419 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
441 if (BaseOp && !BaseOp->isFI()) in getMemOperandsWithOffsetWidth()
442 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
484 if (!BaseOp) // e.g. S_MEMTIME in getMemOperandsWithOffsetWidth()
486 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
500 if (BaseOp) in getMemOperandsWithOffsetWidth()
501 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
503 if (BaseOp) in getMemOperandsWithOffsetWidth()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1365 const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
1373 BaseOp = BaseOps.front(); in getMemOperandWithOffset()
1534 const MachineOperand *BaseOp; in describeLoadedValue() local
1535 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in describeLoadedValue()
1559 return ParamLoadedValue(*BaseOp, Expr); in describeLoadedValue()
H A DMachineSink.cpp1306 const MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
1309 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in SinkingPreventsImplicitNullCheck()
1312 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
1325 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
H A DModuloSchedule.cpp922 const MachineOperand *BaseOp; in computeDelta() local
925 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
932 if (!BaseOp->isReg()) in computeDelta()
935 Register BaseReg = BaseOp->getReg(); in computeDelta()
H A DMachinePipeliner.cpp2514 const MachineOperand *BaseOp; in computeDelta() local
2517 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
2524 if (!BaseOp->isReg()) in computeDelta()
2527 Register BaseReg = BaseOp->getReg(); in computeDelta()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h168 const MachineOperand *&BaseOp,
H A DRISCVInstrInfo.cpp2233 const MachineOperand *BaseOp; in getMemOperandsWithOffsetWidth() local
2235 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
2237 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1573 unsigned BaseOp = 0; in lowerOverflowArithmetic() local
1578 BaseOp = M68kISD::ADD; in lowerOverflowArithmetic()
1582 BaseOp = M68kISD::ADD; in lowerOverflowArithmetic()
1586 BaseOp = M68kISD::SUB; in lowerOverflowArithmetic()
1590 BaseOp = M68kISD::SUB; in lowerOverflowArithmetic()
1596 BaseOp = NoOverflow ? ISD::MUL : M68kISD::UMUL; in lowerOverflowArithmetic()
1602 BaseOp = NoOverflow ? ISD::MUL : M68kISD::SMUL; in lowerOverflowArithmetic()
1614 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerOverflowArithmetic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4253 unsigned BaseOp = 0; in lowerXALUO() local
4259 BaseOp = ISD::ADD; in lowerXALUO()
4263 BaseOp = ISD::SUB; in lowerXALUO()
4279 unsigned BaseOp = 0; in lowerXALUO() local
4286 BaseOp = SystemZISD::SADDO; in lowerXALUO()
4291 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
4296 BaseOp = SystemZISD::UADDO; in lowerXALUO()
4301 BaseOp = SystemZISD::USUBO; in lowerXALUO()
4346 unsigned BaseOp = 0; in lowerUADDSUBO_CARRY() local
4352 BaseOp = SystemZISD::VAC; in lowerUADDSUBO_CARRY()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h545 const MachineOperand *&BaseOp,
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td1788 // let RowFields = BaseOp
1789 // All add instruction predicated/non-predicated will have to set their BaseOp
1792 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1793 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1794 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1434 const MachineOperand *&BaseOp, int64_t &Offset,
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp7491 unsigned BaseOp; in lowerAddSubSatToMinMax() local
7498 BaseOp = TargetOpcode::G_ADD; in lowerAddSubSatToMinMax()
7503 BaseOp = TargetOpcode::G_ADD; in lowerAddSubSatToMinMax()
7508 BaseOp = TargetOpcode::G_SUB; in lowerAddSubSatToMinMax()
7513 BaseOp = TargetOpcode::G_SUB; in lowerAddSubSatToMinMax()
7547 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); in lowerAddSubSatToMinMax()
7553 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); in lowerAddSubSatToMinMax()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp4393 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp() local
4394 if (!BaseOp.isReg()) // Can be an MO_FrameIndex in getAddrModeFromMemoryOp()
4403 AM.BaseReg = BaseOp.getReg(); in getAddrModeFromMemoryOp()
4520 const MachineOperand *BaseOp = in getMemOperandsWithOffsetWidth() local
4522 if (!BaseOp->isReg()) // Can be an MO_FrameIndex in getMemOperandsWithOffsetWidth()
4540 if (!BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
4549 BaseOps.push_back(BaseOp); in getMemOperandsWithOffsetWidth()

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