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Searched refs:BaseOffs (Results 1 – 24 of 24) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1791 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1796 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1803 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1806 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1811 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1814 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1818 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1821 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2718 if (BaseOffs != other.BaseOffs) in compare()
2791 BaseOffs = 0; in SetCombinedField()
2816 if (BaseOffs) { in print()
4194 if (AddrMode.BaseOffs) { in matchScaledValue()
4856 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4862 AddrMode.BaseOffs -= ConstantOffset; in matchOperationAddr()
4894 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4921 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
5549 !AddrMode.BaseOffs) { in optimizeMemoryInst()
5592 if (AddrMode.BaseOffs) { in optimizeMemoryInst()
[all …]
H A DTargetLoweringBase.cpp1971 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1983 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1988 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp260 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
H A DSILoadStoreOptimizer.cpp2217 AM.BaseOffs = Dist; in promoteConstantOffsetToImm()
2242 AM.BaseOffs = P.second - AnchorAddr.Offset; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1451 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode()
1456 AM.BaseOffs, AddrSpace, FlatVariant)); in isLegalFlatAddressingMode()
1492 if (!TII->isLegalMUBUFImmOffset(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
1534 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
1547 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1552 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1556 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1561 if (!isInt<21>(AM.BaseOffs)) in isLegalAddressingMode()
1565 if (!isInt<24>(AM.BaseOffs)) in isLegalAddressingMode()
1590 if (!isUInt<16>(AM.BaseOffs)) in isLegalAddressingMode()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp967 AM.BaseOffs = CstOff->getSExtValue(); // [reg +/- imm] in canFoldInAddressingMode()
1588 AMNew.BaseOffs = CombinedImm.getSExtValue(); in matchPtrAddImmedChain()
1592 AMOld.BaseOffs = MaybeImmVal->Value.getSExtValue(); in matchPtrAddImmedChain()
1602 MatchInfo.Imm = AMNew.BaseOffs; in matchPtrAddImmedChain()
4554 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
4564 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h339 AM.BaseOffs = BaseOffset;
403 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
H A DTargetLowering.h2690 int64_t BaseOffs = 0; member
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp4882 if (!isInt<12>(AM.BaseOffs) || !isShiftedInt<14, 2>(AM.BaseOffs)) in isLegalAddressingMode()
4894 if (AM.HasBaseReg && AM.BaseOffs != 0) in isLegalAddressingMode()
4900 if (AM.HasBaseReg || AM.BaseOffs) in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3661 if (!isAligned(A, AM.BaseOffs)) in isLegalAddressingMode()
3664 if (!isInt<11>(AM.BaseOffs >> Log2(A))) in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp2571 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
H A DARMISelLowering.cpp19649 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
19661 if (AM.BaseOffs) in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1061 int64_t Offs = AM.BaseOffs; in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp790 if (AM.BaseOffs < 0) in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16826 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
16830 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
16842 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
16847 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp4050 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
H A DAArch64ISelLowering.cpp16242 if (AMode.HasBaseReg && AMode.BaseOffs && AMode.Scale) in isLegalAddressingMode()
16268 return AM.HasBaseReg && !AM.BaseOffs && in isLegalAddressingMode()
16272 return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale; in isLegalAddressingMode()
16285 return Subtarget->getInstrInfo()->isLegalAddressingMode(NumBytes, AM.BaseOffs, in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1067 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1076 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1242 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
1250 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
1269 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
2454 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
2463 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4987 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp6676 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
H A DX86ISelLowering.cpp33551 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode()
33568 Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1734 return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs; in isLegalAddressingMode()
1737 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()