Searched refs:BaseIdx (Results 1 – 7 of 7) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | PseudoLoweringEmitter.cpp | 57 unsigned BaseIdx); 74 IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { in addDagOperandMapping() argument 82 OperandMap[BaseIdx + i].Kind = OpData::Reg; in addDagOperandMapping() 83 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); in addDagOperandMapping() 93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) { in addDagOperandMapping() 105 OperandMap[BaseIdx + i + I].Kind = OpData::Operand; in addDagOperandMapping() 108 OperandMap[BaseIdx + i].Kind = OpData::Imm; in addDagOperandMapping() 109 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); in addDagOperandMapping() 114 OperandMap[BaseIdx + i].Kind = OpData::Imm; in addDagOperandMapping() 115 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); in addDagOperandMapping() [all …]
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| /freebsd-14.2/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | Store.cpp | 489 SVal BaseIdx = ElemR->getIndex(); in getLValueElement() local 491 if (!isa<nonloc::ConcreteInt>(BaseIdx)) in getLValueElement() 495 BaseIdx.castAs<nonloc::ConcreteInt>().getValue(); in getLValueElement()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | StackMaps.cpp | 469 unsigned BaseIdx = GCPtrIndices[P.first]; in parseStatepointOpers() local 471 LLVM_DEBUG(dbgs() << "Base : " << BaseIdx << " Derived : " << DerivedIdx in parseStatepointOpers() 473 (void)parseOperand(MOB + BaseIdx, MOE, Locations, LiveOuts); in parseStatepointOpers()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 5559 SDValue BaseIdx = N->getOperand(1); in PromoteIntRes_EXTRACT_SUBVECTOR() local 5573 uint64_t IdxVal = BaseIdx->getAsZExtVal(); in PromoteIntRes_EXTRACT_SUBVECTOR() 5577 BaseIdx.getValueType())); in PromoteIntRes_EXTRACT_SUBVECTOR() 5580 DAG.getConstant(IdxVal % NElts, dl, BaseIdx.getValueType())); in PromoteIntRes_EXTRACT_SUBVECTOR() 5586 SDValue Ops[] = {GetWidenedVector(InOp0), BaseIdx}; in PromoteIntRes_EXTRACT_SUBVECTOR() 5595 SDValue Ops[] = { GetPromotedInteger(InOp0), BaseIdx }; in PromoteIntRes_EXTRACT_SUBVECTOR() 5622 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), in PromoteIntRes_EXTRACT_SUBVECTOR() 5623 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType())); in PromoteIntRes_EXTRACT_SUBVECTOR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | RewriteStatepointsForGC.cpp | 1538 Value *BaseIdx = Builder.getInt32(FindIndex(LiveVariables, BasePtrs[i])); in CreateGCRelocates() local 1548 GCRelocateDecl, {StatepointToken, BaseIdx, LiveIdx}, in CreateGCRelocates()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 553 unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), Align) - Align; in getAlignedHighSGPRForRC() local 554 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in getAlignedHighSGPRForRC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 4872 if (BaseIdx != 0) in getTargetConstantBitsFromNode() 6061 int BaseIdx = i * NumBytesPerElt; in getFauxShuffleMask() local 6833 return (0 <= BaseIdx && BaseIdx < (int)NumElems && LoadMask[BaseIdx] && in EltsFromConsecutiveLoads() 6834 Loads[BaseIdx] == Ld && ByteOffsets[BaseIdx] == 0); in EltsFromConsecutiveLoads() 7627 unsigned ExpectedVExtractIdx = BaseIdx; in isHorizontalBinOpPart() 7628 unsigned NumElts = LastIdx - BaseIdx; in isHorizontalBinOpPart() 7634 SDValue Op = N->getOperand(i + BaseIdx); in isHorizontalBinOpPart() 7640 ExpectedVExtractIdx = BaseIdx; in isHorizontalBinOpPart() 7679 ExpectedVExtractIdx = BaseIdx; in isHorizontalBinOpPart() 38985 if (isInRange(M, BaseIdx, BaseIdx + RootMask.size())) in combineX86ShufflesRecursively() [all …]
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