Searched refs:BaseDef (Results 1 – 5 of 5) sorted by relevance
500 Record *BaseDef = in addEntryWithFlags() local503 BaseDef ? Target.getInstruction(BaseDef).isMoveReg : RegInst->isMoveReg; in addEntryWithFlags()506 if (IsMoveReg && (BaseDef || Result.FoldStore)) in addEntryWithFlags()
939 MachineInstr *BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() local940 if (BaseDef && BaseDef->isPHI()) { in computeDelta()941 BaseReg = getLoopPhiReg(*BaseDef, MI.getParent()); in computeDelta()942 BaseDef = MRI.getVRegDef(BaseReg); in computeDelta()944 if (!BaseDef) in computeDelta()948 if (!TII->getIncrementValue(*BaseDef, D) && D >= 0) in computeDelta()
2531 MachineInstr *BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() local2532 if (BaseDef && BaseDef->isPHI()) { in computeDelta()2533 BaseReg = getLoopPhiReg(*BaseDef, MI.getParent()); in computeDelta()2534 BaseDef = MRI.getVRegDef(BaseReg); in computeDelta()2536 if (!BaseDef) in computeDelta()2540 if (!TII->getIncrementValue(*BaseDef, D) && D >= 0) in computeDelta()
4823 std::optional<DefinitionAndSourceRegister> BaseDef = in isFlatScratchBaseLegalSVImm() local4833 if (isNoUnsignedWrap(BaseDef->MI) && in isFlatScratchBaseLegalSVImm()4839 Register LHS = BaseDef->MI->getOperand(1).getReg(); in isFlatScratchBaseLegalSVImm()4840 Register RHS = BaseDef->MI->getOperand(2).getReg(); in isFlatScratchBaseLegalSVImm()
1129 MachineInstr *BaseDef = getDefIgnoringCopies(Base, MRI); in findPreIndexCandidate() local1130 if (BaseDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) in findPreIndexCandidate()