| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MachineScheduler.cpp | 39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite() local
42 if (!Base0.isIdenticalTo(Base1)) in mayOverlapWrite()
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| /freebsd-14.2/contrib/llvm-project/clang/lib/AST/ |
| H A D | ASTStructuralEquivalence.cpp | 1692 for (CXXRecordDecl::base_class_iterator Base1 = D1CXX->bases_begin(), in IsStructurallyEquivalent() local
1695 Base1 != BaseEnd1; ++Base1, ++Base2) { in IsStructurallyEquivalent()
1696 if (!IsStructurallyEquivalent(Context, Base1->getType(), in IsStructurallyEquivalent()
1705 Context.Diag1(Base1->getBeginLoc(), diag::note_odr_base) in IsStructurallyEquivalent()
1706 << Base1->getType() << Base1->getSourceRange(); in IsStructurallyEquivalent()
1712 if (Base1->isVirtual() != Base2->isVirtual()) { in IsStructurallyEquivalent()
1720 Context.Diag1(Base1->getBeginLoc(), diag::note_odr_base) in IsStructurallyEquivalent()
1721 << Base1->isVirtual() << Base1->getSourceRange(); in IsStructurallyEquivalent()
1775 const CXXBaseSpecifier *Base1 = D1CXX->bases_begin(); in IsStructurallyEquivalent() local
1776 Context.Diag1(Base1->getBeginLoc(), diag::note_odr_base) in IsStructurallyEquivalent()
[all …]
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| H A D | ASTImporter.cpp | 2240 for (const auto &Base1 : FromCXX->bases()) { in ImportDefinition() local
2241 ExpectedType TyOrErr = import(Base1.getType()); in ImportDefinition()
2246 if (Base1.isPackExpansion()) { in ImportDefinition()
2247 if (ExpectedSLoc LocOrErr = import(Base1.getEllipsisLoc())) in ImportDefinition()
2255 ImportDefinitionIfNeeded(Base1.getType()->getAsCXXRecordDecl())) in ImportDefinition()
2258 auto RangeOrErr = import(Base1.getSourceRange()); in ImportDefinition()
2262 auto TSIOrErr = import(Base1.getTypeSourceInfo()); in ImportDefinition()
2269 Base1.isVirtual(), in ImportDefinition()
2270 Base1.isBaseOfClass(), in ImportDefinition()
2271 Base1.getAccessSpecifierAsWritten(), in ImportDefinition()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2261 auto Base1 = MO1->getValue(); in memOpsHaveSameBasePtr() local
2263 if (!Base1 || !Base2) in memOpsHaveSameBasePtr()
2265 Base1 = getUnderlyingObject(Base1); in memOpsHaveSameBasePtr()
2268 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2)) in memOpsHaveSameBasePtr()
2271 return Base1 == Base2; in memOpsHaveSameBasePtr()
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| H A D | RISCVISelLowering.cpp | 13780 auto [Base1, Offset1] = ExtractBaseAndOffset(LSNode1->getOperand(OpNum)); in performMemPairCombine()
13806 if (Base1 != Base2) in performMemPairCombine()
13826 tryMemPairCombine(DAG, LSNode1, LSNode2, Base1, Offset1)) in performMemPairCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 2977 SDValue Base1 = in SplitHvxMemOp() local
2994 SDValue Load1 = DAG.getLoad(SingleTy, dl, Chain, Base1, MOp1); in SplitHvxMemOp()
3004 SDValue Store1 = DAG.getStore(Chain, dl, Vals.second, Base1, MOp1); in SplitHvxMemOp()
3023 DAG.getMaskedLoad(SingleTy, dl, Chain, Base1, Offset, Masks.second, in SplitHvxMemOp()
3036 SDValue MStore1 = DAG.getMaskedStore(Chain, dl, Vals.second, Base1, Offset, in SplitHvxMemOp()
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| H A D | HexagonISelLowering.cpp | 3217 SDValue Base1 = DAG.getMemBasePlusOffset( in LowerUnalignedLoad() local
3230 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO); in LowerUnalignedLoad()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 537 auto Base1 = MO1->getValue(); in memOpsHaveSameBasePtr() local
539 if (!Base1 || !Base2) in memOpsHaveSameBasePtr()
541 Base1 = getUnderlyingObject(Base1); in memOpsHaveSameBasePtr()
544 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2)) in memOpsHaveSameBasePtr()
547 return Base1 == Base2; in memOpsHaveSameBasePtr()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2916 const MachineOperand *Base1 = nullptr, *Base2 = nullptr; in shouldClusterMemOps() local
2917 if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) || in shouldClusterMemOps()
2922 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 && in shouldClusterMemOps()
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| H A D | PPCISelLowering.cpp | 13621 SDValue Base1 = Loc, Base2 = BaseLoc; in isConsecutiveLSLoc() local
13623 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG); in isConsecutiveLSLoc()
13625 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes)) in isConsecutiveLSLoc()
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| /freebsd-14.2/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaChecking.cpp | 19077 Base1 = D1CXX->bases_begin(), in isLayoutCompatibleStruct() local
19080 Base1 != BaseEnd1; in isLayoutCompatibleStruct()
19081 ++Base1, ++Base2) { in isLayoutCompatibleStruct()
19082 if (!isLayoutCompatible(C, Base1->getType(), Base2->getType())) in isLayoutCompatibleStruct()
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