| /freebsd-14.2/sys/contrib/device-tree/src/arm64/allwinner/ |
| H A D | sun50i-h616-x96-mate.dts | 101 /* Enabled by the Android BSP */
109 /* Enabled by the Android BSP */
124 /* Enabled by the Android BSP */
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| /freebsd-14.2/usr.sbin/bhyve/ |
| H A D | bhyverun.c | 105 static const int BSP = 0; variable
476 if (vcpu != BSP) { in fbsdrun_deletecpu()
898 bsp = vm_vcpu_open(ctx, BSP); in main()
913 if (vcpuid == BSP) in main()
975 bhyve_start_vcpu(vcpu_info[vcpuid].vcpu, vcpuid == BSP); in main()
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| /freebsd-14.2/usr.sbin/bhyveload/ |
| H A D | bhyveload.c | 88 #define BSP 0 macro
610 assert(vcpuid == BSP); in cb_vm_set_register()
619 assert(vcpuid == BSP); in cb_vm_set_desc()
894 vcpu = vm_vcpu_open(ctx, BSP); in main()
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| /freebsd-14.2/sys/contrib/device-tree/src/powerpc/ |
| H A D | mpc5125twr.dts | 16 model = "mpc5125twr"; // In BSP "mpc5125ads"
287 compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
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| /freebsd-14.2/sys/powerpc/powerpc/ |
| H A D | platform_if.m | 254 * Entered (approximately) simultaneously on all CPUs, including the BSP.
255 * Passed the timebase value on the BSP as of shortly before the call.
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| /freebsd-14.2/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3399pro-vmarc-som.dtsi | 204 * As per BSP, but schematic not showing any regulator
252 * As per BSP, but schematic not showing any regulator
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| H A D | rk3566-anbernic-rgxx3.dtsi | 70 * Button is mapped to F key in BSP kernel, but
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/arm/bcm/ |
| H A D | brcm,brcmstb.txt | 78 A phandle / integer array property which lets the BSP know the location
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrGISel.td | 266 // Generic instruction for the BSP pseudo. It is expanded into BSP, which
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| H A D | AArch64ISelLowering.h | 195 BSP, enumerator
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| H A D | AArch64SchedFalkorDetails.td | 914 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v8i8$")>;
938 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v16i8$")>;
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| H A D | AArch64SchedCyclone.td | 502 // BIF,BIT,BSL,BSP
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| H A D | AArch64SchedExynosM3.td | 668 def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
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| H A D | AArch64SchedA57.td | 527 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>;
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| H A D | AArch64SchedExynosM4.td | 811 def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
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| H A D | AArch64SchedExynosM5.td | 849 def : InstRW<[M5WriteNALU2], (instregex "^(BIF|BIT|BSL|BSP)v")>;
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| H A D | AArch64ISelLowering.cpp | 2443 MAKE_CASE(AArch64ISD::BSP) in getTargetNodeName()
9097 SDValue BSP = in LowerFCOPYSIGN() local
9098 DAG.getNode(AArch64ISD::BSP, DL, VecVT, SignMaskV, VecVal1, VecVal2); in LowerFCOPYSIGN()
9100 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, BSP); in LowerFCOPYSIGN()
9102 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, BSP); in LowerFCOPYSIGN()
9104 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, BSP); in LowerFCOPYSIGN()
9106 return BitCast(VT, BSP, DAG); in LowerFCOPYSIGN()
17525 return DAG.getNode(AArch64ISD::BSP, DL, VT, Sub, SubSibling, AddSibling); in tryCombineToBSL()
17553 return DAG.getNode(AArch64ISD::BSP, DL, VT, SDValue(BVN0, 0), in tryCombineToBSL()
23974 case AArch64ISD::BSP: in PerformDAGCombine()
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| H A D | AArch64InstrInfo.td | 734 def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>;
5270 // Pseudo bitwise select pattern BSP.
5272 defm BSP : SIMDLogicalThreeVectorPseudo<TriOpFrag<(or (and node:$LHS, node:$MHS),
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| H A D | SVEInstrFormats.td | 608 // Used to re-order the operands of BSP when lowering to BSL. BSP has the order:
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| /freebsd-14.2/contrib/file/magic/Magdir/ |
| H A D | games | 19 >4 long 0x26 II Map file (BSP)
20 >4 long 0x2E III Map file (BSP)
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