1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Daisuke Aoyama <[email protected]>
5 * Copyright (c) 2013 Oleksandr Tymoshenko <[email protected]>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/queue.h>
40 #include <sys/resource.h>
41 #include <sys/rman.h>
42
43 #include <dev/ofw/openfirm.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include <vm/vm.h>
48 #include <vm/pmap.h>
49 #include <machine/bus.h>
50
51 #include "bcm2835_dma.h"
52 #include "bcm2835_vcbus.h"
53
54 #define MAX_REG 9
55
56 /* private flags */
57 #define BCM_DMA_CH_USED 0x00000001
58 #define BCM_DMA_CH_FREE 0x40000000
59 #define BCM_DMA_CH_UNMAP 0x80000000
60
61 /* Register Map (4.2.1.2) */
62 #define BCM_DMA_CS(n) (0x100*(n) + 0x00)
63 #define CS_ACTIVE (1 << 0)
64 #define CS_END (1 << 1)
65 #define CS_INT (1 << 2)
66 #define CS_DREQ (1 << 3)
67 #define CS_ISPAUSED (1 << 4)
68 #define CS_ISHELD (1 << 5)
69 #define CS_ISWAIT (1 << 6)
70 #define CS_ERR (1 << 8)
71 #define CS_WAITWRT (1 << 28)
72 #define CS_DISDBG (1 << 29)
73 #define CS_ABORT (1 << 30)
74 #define CS_RESET (1U << 31)
75 #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04)
76 #define BCM_DMA_INFO(n) (0x100*(n) + 0x08)
77 #define INFO_INT_EN (1 << 0)
78 #define INFO_TDMODE (1 << 1)
79 #define INFO_WAIT_RESP (1 << 3)
80 #define INFO_D_INC (1 << 4)
81 #define INFO_D_WIDTH (1 << 5)
82 #define INFO_D_DREQ (1 << 6)
83 #define INFO_S_INC (1 << 8)
84 #define INFO_S_WIDTH (1 << 9)
85 #define INFO_S_DREQ (1 << 10)
86 #define INFO_WAITS_SHIFT (21)
87 #define INFO_PERMAP_SHIFT (16)
88 #define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT)
89
90 #define BCM_DMA_SRC(n) (0x100*(n) + 0x0C)
91 #define BCM_DMA_DST(n) (0x100*(n) + 0x10)
92 #define BCM_DMA_LEN(n) (0x100*(n) + 0x14)
93 #define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18)
94 #define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C)
95 #define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20)
96 #define DEBUG_ERROR_MASK (7)
97
98 #define BCM_DMA_INT_STATUS 0xfe0
99 #define BCM_DMA_ENABLE 0xff0
100
101 /* relative offset from BCM_VC_DMA0_BASE (p.39) */
102 #define BCM_DMA_CH(n) (0x100*(n))
103
104 /* channels used by GPU */
105 #define BCM_DMA_CH_BULK 0
106 #define BCM_DMA_CH_FAST1 2
107 #define BCM_DMA_CH_FAST2 3
108
109 #define BCM_DMA_CH_GPU_MASK ((1 << BCM_DMA_CH_BULK) | \
110 (1 << BCM_DMA_CH_FAST1) | \
111 (1 << BCM_DMA_CH_FAST2))
112
113 /* DMA Control Block - 256bit aligned (p.40) */
114 struct bcm_dma_cb {
115 uint32_t info; /* Transfer Information */
116 uint32_t src; /* Source Address */
117 uint32_t dst; /* Destination Address */
118 uint32_t len; /* Transfer Length */
119 uint32_t stride; /* 2D Mode Stride */
120 uint32_t next; /* Next Control Block Address */
121 uint32_t rsvd1; /* Reserved */
122 uint32_t rsvd2; /* Reserved */
123 };
124
125 #ifdef DEBUG
126 static void bcm_dma_cb_dump(struct bcm_dma_cb *cb);
127 static void bcm_dma_reg_dump(int ch);
128 #endif
129
130 /* DMA channel private info */
131 struct bcm_dma_ch {
132 int ch;
133 uint32_t flags;
134 struct bcm_dma_cb * cb;
135 uint32_t vc_cb;
136 bus_dmamap_t dma_map;
137 void (*intr_func)(int, void *);
138 void * intr_arg;
139 };
140
141 struct bcm_dma_softc {
142 device_t sc_dev;
143 struct mtx sc_mtx;
144 struct resource * sc_mem;
145 struct resource * sc_irq[BCM_DMA_CH_MAX];
146 void * sc_intrhand[BCM_DMA_CH_MAX];
147 struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX];
148 bus_dma_tag_t sc_dma_tag;
149 };
150
151 static struct bcm_dma_softc *bcm_dma_sc = NULL;
152 static uint32_t bcm_dma_channel_mask;
153
154 static struct ofw_compat_data compat_data[] = {
155 {"broadcom,bcm2835-dma", 1},
156 {"brcm,bcm2835-dma", 1},
157 {NULL, 0}
158 };
159
160 static void
bcm_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int err)161 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
162 int nseg, int err)
163 {
164 bus_addr_t *addr;
165
166 if (err)
167 return;
168
169 addr = (bus_addr_t*)arg;
170 *addr = ARMC_TO_VCBUS(segs[0].ds_addr);
171 }
172
173 static void
bcm_dma_reset(device_t dev,int ch)174 bcm_dma_reset(device_t dev, int ch)
175 {
176 struct bcm_dma_softc *sc = device_get_softc(dev);
177 struct bcm_dma_cb *cb;
178 uint32_t cs;
179 int count;
180
181 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
182 return;
183
184 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
185
186 if (cs & CS_ACTIVE) {
187 /* pause current task */
188 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0);
189
190 count = 1000;
191 do {
192 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
193 } while (!(cs & CS_ISPAUSED) && (count-- > 0));
194
195 if (!(cs & CS_ISPAUSED)) {
196 device_printf(dev,
197 "Can't abort DMA transfer at channel %d\n", ch);
198 }
199
200 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
201
202 /* Complete everything, clear interrupt */
203 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch),
204 CS_ABORT | CS_INT | CS_END| CS_ACTIVE);
205 }
206
207 /* clear control blocks */
208 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0);
209 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
210
211 /* Reset control block */
212 cb = sc->sc_dma_ch[ch].cb;
213 bzero(cb, sizeof(*cb));
214 cb->info = INFO_WAIT_RESP;
215 }
216
217 static int
bcm_dma_init(device_t dev)218 bcm_dma_init(device_t dev)
219 {
220 struct bcm_dma_softc *sc = device_get_softc(dev);
221 uint32_t reg;
222 struct bcm_dma_ch *ch;
223 void *cb_virt;
224 vm_paddr_t cb_phys;
225 int err;
226 int i;
227
228 /*
229 * Only channels set in bcm_dma_channel_mask can be controlled by us.
230 * The others are out of our control as well as the corresponding bits
231 * in both BCM_DMA_ENABLE and BCM_DMA_INT_STATUS global registers. As
232 * these registers are RW ones, there is no safe way how to write only
233 * the bits which can be controlled by us.
234 *
235 * Fortunately, after reset, all channels are enabled in BCM_DMA_ENABLE
236 * register and all statuses are cleared in BCM_DMA_INT_STATUS one.
237 * Not touching these registers is a trade off between correct
238 * initialization which does not count on anything and not messing up
239 * something we have no control over.
240 */
241 reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE);
242 if ((reg & bcm_dma_channel_mask) != bcm_dma_channel_mask)
243 device_printf(dev, "channels are not enabled\n");
244 reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS);
245 if ((reg & bcm_dma_channel_mask) != 0)
246 device_printf(dev, "statuses are not cleared\n");
247
248 /*
249 * Allocate DMA chunks control blocks based on p.40 of the peripheral
250 * spec - control block should be 32-bit aligned. The DMA controller
251 * has a full 32-bit register dedicated to this address, so we do not
252 * need to bother with the per-SoC peripheral restrictions.
253 */
254 err = bus_dma_tag_create(bus_get_dma_tag(dev),
255 1, 0, BUS_SPACE_MAXADDR_32BIT,
256 BUS_SPACE_MAXADDR, NULL, NULL,
257 sizeof(struct bcm_dma_cb), 1,
258 sizeof(struct bcm_dma_cb),
259 BUS_DMA_ALLOCNOW, NULL, NULL,
260 &sc->sc_dma_tag);
261
262 if (err) {
263 device_printf(dev, "failed allocate DMA tag\n");
264 return (err);
265 }
266
267 /* setup initial settings */
268 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
269 ch = &sc->sc_dma_ch[i];
270
271 bzero(ch, sizeof(struct bcm_dma_ch));
272 ch->ch = i;
273 ch->flags = BCM_DMA_CH_UNMAP;
274
275 if ((bcm_dma_channel_mask & (1 << i)) == 0)
276 continue;
277
278 err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt,
279 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
280 &ch->dma_map);
281 if (err) {
282 device_printf(dev, "cannot allocate DMA memory\n");
283 break;
284 }
285
286 /*
287 * Least alignment for busdma-allocated stuff is cache
288 * line size, so just make sure nothing stupid happened
289 * and we got properly aligned address
290 */
291 if ((uintptr_t)cb_virt & 0x1f) {
292 device_printf(dev,
293 "DMA address is not 32-bytes aligned: %p\n",
294 (void*)cb_virt);
295 break;
296 }
297
298 err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt,
299 sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys,
300 BUS_DMA_WAITOK);
301 if (err) {
302 device_printf(dev, "cannot load DMA memory\n");
303 break;
304 }
305
306 ch->cb = cb_virt;
307 ch->vc_cb = cb_phys;
308 ch->flags = BCM_DMA_CH_FREE;
309 ch->cb->info = INFO_WAIT_RESP;
310
311 /* reset DMA engine */
312 bus_write_4(sc->sc_mem, BCM_DMA_CS(i), CS_RESET);
313 }
314
315 return (0);
316 }
317
318 /*
319 * Allocate DMA channel for further use, returns channel # or
320 * BCM_DMA_CH_INVALID
321 */
322 int
bcm_dma_allocate(int req_ch)323 bcm_dma_allocate(int req_ch)
324 {
325 struct bcm_dma_softc *sc = bcm_dma_sc;
326 int ch = BCM_DMA_CH_INVALID;
327 int i;
328
329 if (sc == NULL)
330 return (BCM_DMA_CH_INVALID);
331
332 if (req_ch >= BCM_DMA_CH_MAX)
333 return (BCM_DMA_CH_INVALID);
334
335 /* Auto(req_ch < 0) or CH specified */
336 mtx_lock(&sc->sc_mtx);
337
338 if (req_ch < 0) {
339 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
340 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) {
341 ch = i;
342 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
343 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
344 break;
345 }
346 }
347 } else if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) {
348 ch = req_ch;
349 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
350 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
351 }
352
353 mtx_unlock(&sc->sc_mtx);
354 return (ch);
355 }
356
357 /*
358 * Frees allocated channel. Returns 0 on success, -1 otherwise
359 */
360 int
bcm_dma_free(int ch)361 bcm_dma_free(int ch)
362 {
363 struct bcm_dma_softc *sc = bcm_dma_sc;
364
365 if (sc == NULL)
366 return (-1);
367
368 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
369 return (-1);
370
371 mtx_lock(&sc->sc_mtx);
372 if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) {
373 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE;
374 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED;
375 sc->sc_dma_ch[ch].intr_func = NULL;
376 sc->sc_dma_ch[ch].intr_arg = NULL;
377
378 /* reset DMA engine */
379 bcm_dma_reset(sc->sc_dev, ch);
380 }
381
382 mtx_unlock(&sc->sc_mtx);
383 return (0);
384 }
385
386 /*
387 * Assign handler function for channel interrupt
388 * Returns 0 on success, -1 otherwise
389 */
390 int
bcm_dma_setup_intr(int ch,void (* func)(int,void *),void * arg)391 bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg)
392 {
393 struct bcm_dma_softc *sc = bcm_dma_sc;
394 struct bcm_dma_cb *cb;
395
396 if (sc == NULL)
397 return (-1);
398
399 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
400 return (-1);
401
402 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
403 return (-1);
404
405 sc->sc_dma_ch[ch].intr_func = func;
406 sc->sc_dma_ch[ch].intr_arg = arg;
407 cb = sc->sc_dma_ch[ch].cb;
408 cb->info |= INFO_INT_EN;
409
410 return (0);
411 }
412
413 /*
414 * Setup DMA source parameters
415 * ch - channel number
416 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
417 * source is physical memory
418 * inc_addr - BCM_DMA_INC_ADDR if source address
419 * should be increased after each access or
420 * BCM_DMA_SAME_ADDR if address should remain
421 * the same
422 * width - size of read operation, BCM_DMA_32BIT
423 * for 32bit bursts, BCM_DMA_128BIT for 128 bits
424 *
425 * Returns 0 on success, -1 otherwise
426 */
427 int
bcm_dma_setup_src(int ch,int dreq,int inc_addr,int width)428 bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width)
429 {
430 struct bcm_dma_softc *sc = bcm_dma_sc;
431 uint32_t info;
432
433 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
434 return (-1);
435
436 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
437 return (-1);
438
439 info = sc->sc_dma_ch[ch].cb->info;
440 info &= ~INFO_PERMAP_MASK;
441 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
442
443 if (dreq)
444 info |= INFO_S_DREQ;
445 else
446 info &= ~INFO_S_DREQ;
447
448 if (width == BCM_DMA_128BIT)
449 info |= INFO_S_WIDTH;
450 else
451 info &= ~INFO_S_WIDTH;
452
453 if (inc_addr == BCM_DMA_INC_ADDR)
454 info |= INFO_S_INC;
455 else
456 info &= ~INFO_S_INC;
457
458 sc->sc_dma_ch[ch].cb->info = info;
459
460 return (0);
461 }
462
463 /*
464 * Setup DMA destination parameters
465 * ch - channel number
466 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
467 * destination is physical memory
468 * inc_addr - BCM_DMA_INC_ADDR if source address
469 * should be increased after each access or
470 * BCM_DMA_SAME_ADDR if address should remain
471 * the same
472 * width - size of write operation, BCM_DMA_32BIT
473 * for 32bit bursts, BCM_DMA_128BIT for 128 bits
474 *
475 * Returns 0 on success, -1 otherwise
476 */
477 int
bcm_dma_setup_dst(int ch,int dreq,int inc_addr,int width)478 bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width)
479 {
480 struct bcm_dma_softc *sc = bcm_dma_sc;
481 uint32_t info;
482
483 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
484 return (-1);
485
486 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
487 return (-1);
488
489 info = sc->sc_dma_ch[ch].cb->info;
490 info &= ~INFO_PERMAP_MASK;
491 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
492
493 if (dreq)
494 info |= INFO_D_DREQ;
495 else
496 info &= ~INFO_D_DREQ;
497
498 if (width == BCM_DMA_128BIT)
499 info |= INFO_D_WIDTH;
500 else
501 info &= ~INFO_D_WIDTH;
502
503 if (inc_addr == BCM_DMA_INC_ADDR)
504 info |= INFO_D_INC;
505 else
506 info &= ~INFO_D_INC;
507
508 sc->sc_dma_ch[ch].cb->info = info;
509
510 return (0);
511 }
512
513 #ifdef DEBUG
514 void
bcm_dma_cb_dump(struct bcm_dma_cb * cb)515 bcm_dma_cb_dump(struct bcm_dma_cb *cb)
516 {
517
518 printf("DMA CB ");
519 printf("INFO: %8.8x ", cb->info);
520 printf("SRC: %8.8x ", cb->src);
521 printf("DST: %8.8x ", cb->dst);
522 printf("LEN: %8.8x ", cb->len);
523 printf("\n");
524 printf("STRIDE: %8.8x ", cb->stride);
525 printf("NEXT: %8.8x ", cb->next);
526 printf("RSVD1: %8.8x ", cb->rsvd1);
527 printf("RSVD2: %8.8x ", cb->rsvd2);
528 printf("\n");
529 }
530
531 void
bcm_dma_reg_dump(int ch)532 bcm_dma_reg_dump(int ch)
533 {
534 struct bcm_dma_softc *sc = bcm_dma_sc;
535 int i;
536 uint32_t reg;
537
538 if (sc == NULL)
539 return;
540
541 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
542 return;
543
544 printf("DMA%d: ", ch);
545 for (i = 0; i < MAX_REG; i++) {
546 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4);
547 printf("%8.8x ", reg);
548 }
549 printf("\n");
550 }
551 #endif
552
553 /*
554 * Start DMA transaction
555 * ch - channel number
556 * src, dst - source and destination address in
557 * ARM physical memory address space.
558 * len - amount of bytes to be transferred
559 *
560 * Returns 0 on success, -1 otherwise
561 */
562 int
bcm_dma_start(int ch,vm_paddr_t src,vm_paddr_t dst,int len)563 bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len)
564 {
565 struct bcm_dma_softc *sc = bcm_dma_sc;
566 struct bcm_dma_cb *cb;
567
568 if (sc == NULL)
569 return (-1);
570
571 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
572 return (-1);
573
574 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
575 return (-1);
576
577 cb = sc->sc_dma_ch[ch].cb;
578 cb->src = ARMC_TO_VCBUS(src);
579 cb->dst = ARMC_TO_VCBUS(dst);
580
581 cb->len = len;
582
583 bus_dmamap_sync(sc->sc_dma_tag,
584 sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE);
585
586 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch),
587 sc->sc_dma_ch[ch].vc_cb);
588 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE);
589
590 #ifdef DEBUG
591 bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb);
592 bcm_dma_reg_dump(ch);
593 #endif
594
595 return (0);
596 }
597
598 /*
599 * Get length requested for DMA transaction
600 * ch - channel number
601 *
602 * Returns size of transaction, 0 if channel is invalid
603 */
604 uint32_t
bcm_dma_length(int ch)605 bcm_dma_length(int ch)
606 {
607 struct bcm_dma_softc *sc = bcm_dma_sc;
608 struct bcm_dma_cb *cb;
609
610 if (sc == NULL)
611 return (0);
612
613 if (ch < 0 || ch >= BCM_DMA_CH_MAX)
614 return (0);
615
616 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
617 return (0);
618
619 cb = sc->sc_dma_ch[ch].cb;
620
621 return (cb->len);
622 }
623
624 static void
bcm_dma_intr(void * arg)625 bcm_dma_intr(void *arg)
626 {
627 struct bcm_dma_softc *sc = bcm_dma_sc;
628 struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg;
629 uint32_t cs, debug;
630
631 /* my interrupt? */
632 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch));
633
634 /*
635 * Is it an active channel? Our diagnostics could be better here, but
636 * it's not necessarily an easy task to resolve a rid/resource to an
637 * actual irq number. We'd want to do this to set a flag indicating
638 * whether the irq is shared or not, so we know to complain.
639 */
640 if (!(ch->flags & BCM_DMA_CH_USED))
641 return;
642
643 /* Again, we can't complain here. The same logic applies. */
644 if (!(cs & (CS_INT | CS_ERR)))
645 return;
646
647 if (cs & CS_ERR) {
648 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch));
649 device_printf(sc->sc_dev, "DMA error %d on CH%d\n",
650 debug & DEBUG_ERROR_MASK, ch->ch);
651 bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch),
652 debug & DEBUG_ERROR_MASK);
653 bcm_dma_reset(sc->sc_dev, ch->ch);
654 }
655
656 if (cs & CS_INT) {
657 /* acknowledge interrupt */
658 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch),
659 CS_INT | CS_END);
660
661 /* Prepare for possible access to len field */
662 bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map,
663 BUS_DMASYNC_POSTWRITE);
664
665 /* save callback function and argument */
666 if (ch->intr_func)
667 ch->intr_func(ch->ch, ch->intr_arg);
668 }
669 }
670
671 static int
bcm_dma_probe(device_t dev)672 bcm_dma_probe(device_t dev)
673 {
674
675 if (!ofw_bus_status_okay(dev))
676 return (ENXIO);
677
678 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
679 return (ENXIO);
680
681 device_set_desc(dev, "BCM2835 DMA Controller");
682 return (BUS_PROBE_DEFAULT);
683 }
684
685 static int
bcm_dma_attach(device_t dev)686 bcm_dma_attach(device_t dev)
687 {
688 struct bcm_dma_softc *sc = device_get_softc(dev);
689 phandle_t node;
690 int rid, err = 0;
691 int i;
692
693 sc->sc_dev = dev;
694
695 if (bcm_dma_sc)
696 return (ENXIO);
697
698 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
699 sc->sc_irq[i] = NULL;
700 sc->sc_intrhand[i] = NULL;
701 }
702
703 /* Get DMA channel mask. */
704 node = ofw_bus_get_node(sc->sc_dev);
705 if (OF_getencprop(node, "brcm,dma-channel-mask", &bcm_dma_channel_mask,
706 sizeof(bcm_dma_channel_mask)) == -1 &&
707 OF_getencprop(node, "broadcom,channels", &bcm_dma_channel_mask,
708 sizeof(bcm_dma_channel_mask)) == -1) {
709 device_printf(dev, "could not get channel mask property\n");
710 return (ENXIO);
711 }
712
713 /* Mask out channels used by GPU. */
714 bcm_dma_channel_mask &= ~BCM_DMA_CH_GPU_MASK;
715
716 /* DMA0 - DMA14 */
717 rid = 0;
718 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
719 if (sc->sc_mem == NULL) {
720 device_printf(dev, "could not allocate memory resource\n");
721 return (ENXIO);
722 }
723
724 /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */
725 for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) {
726 if ((bcm_dma_channel_mask & (1 << rid)) == 0)
727 continue;
728
729 sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
730 RF_ACTIVE | RF_SHAREABLE);
731 if (sc->sc_irq[rid] == NULL) {
732 device_printf(dev, "cannot allocate interrupt\n");
733 err = ENXIO;
734 goto fail;
735 }
736 if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE,
737 NULL, bcm_dma_intr, &sc->sc_dma_ch[rid],
738 &sc->sc_intrhand[rid])) {
739 device_printf(dev, "cannot setup interrupt handler\n");
740 err = ENXIO;
741 goto fail;
742 }
743 }
744
745 mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF);
746 bcm_dma_sc = sc;
747
748 err = bcm_dma_init(dev);
749 if (err)
750 goto fail;
751
752 return (err);
753
754 fail:
755 if (sc->sc_mem)
756 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem);
757
758 for (i = 0; i < BCM_DMA_CH_MAX; i++) {
759 if (sc->sc_intrhand[i])
760 bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]);
761 if (sc->sc_irq[i])
762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]);
763 }
764
765 return (err);
766 }
767
768 static device_method_t bcm_dma_methods[] = {
769 DEVMETHOD(device_probe, bcm_dma_probe),
770 DEVMETHOD(device_attach, bcm_dma_attach),
771 { 0, 0 }
772 };
773
774 static driver_t bcm_dma_driver = {
775 "bcm_dma",
776 bcm_dma_methods,
777 sizeof(struct bcm_dma_softc),
778 };
779
780 EARLY_DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, 0, 0,
781 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
782 MODULE_VERSION(bcm_dma, 1);
783