| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 62 AssertZext, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 580 Lo = DAG.getNode(ISD::AssertZext, dl, L.getValueType(), L, N->getOperand(1)); in SplitVecRes_AssertZext()
581 Hi = DAG.getNode(ISD::AssertZext, dl, H.getValueType(), H, N->getOperand(1)); in SplitVecRes_AssertZext()
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| H A D | SelectionDAGDumper.cpp | 112 case ISD::AssertZext: return "AssertZext"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 60 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
333 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
771 ? ISD::AssertZext in PromoteIntRes_FP_TO_XINT()
2623 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
3548 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
3552 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
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| H A D | SelectionDAGBuilder.cpp | 938 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
5719 case ISD::AssertZext: in getUnderlyingArgRegs()
9882 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, in lowerRangeToAssertZExt()
10643 AssertOp = ISD::AssertZext; in LowerCallTo()
11204 AssertOp = ISD::AssertZext; in LowerArguments()
11244 if (Res.getOpcode() == ISD::AssertZext) in LowerArguments()
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| H A D | LegalizeVectorOps.cpp | 854 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT()
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| H A D | LegalizeVectorTypes.cpp | 991 case ISD::AssertZext: SplitVecRes_AssertZext(N, Lo, Hi); break; in SplitVectorResult()
4074 case ISD::AssertZext: Res = WidenVecRes_AssertZext(N); break; in WidenVectorResult()
5328 return DAG.getNode(ISD::AssertZext, SDLoc(N), InOp.getValueType(), InOp, in WidenVecRes_AssertZext()
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| H A D | LegalizeDAG.cpp | 776 Result = DAG.getNode(ISD::AssertZext, dl, in LegalizeLoadOps()
3126 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res, in ExpandNode()
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| H A D | SelectionDAGISel.cpp | 3085 case ISD::AssertZext: in SelectCodeCommon()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 799 def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
800 class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
827 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
828 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
829 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
830 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
831 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
832 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
833 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
834 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
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| H A D | HexagonISelDAGToDAG.cpp | 1581 case ISD::AssertZext: in keepsLowBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragments.td | 663 // be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying
672 N->getOpcode() != ISD::AssertZext &&
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| H A D | X86ISelLoweringCall.cpp | 1779 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
2618 Op == ISD::AssertZext) { in MatchingStackOffset()
2624 if (TruncInput.getOpcode() == ISD::AssertZext && in MatchingStackOffset()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 374 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 1965 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
2964 NewArg = DAG.getNode(ISD::AssertZext, DL, NewArg.getValueType(), NewArg, in LowerFormalArguments()
3001 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
3020 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
3206 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
7266 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
7955 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Val, in lowerWorkitemID()
11353 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE, in performAndCombine()
11733 case ISD::AssertZext: in calculateByteProvider()
11738 Op->getOpcode() == ISD::AssertZext || in calculateByteProvider()
[all …]
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| H A D | AMDGPUISelLowering.cpp | 576 ISD::FABS, ISD::AssertZext, in AMDGPUTargetLowering()
5194 case ISD::AssertZext: in PerformDAGCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 472 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 482 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
829 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 312 if (TruncInput.getOpcode() == ISD::AssertZext && in MatchingStackOffset()
963 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 492 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL}); in MipsTargetLowering()
3553 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3615 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1462 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
4270 Flag = DAG.getNode(ISD::AssertZext, DL, MVT::i128, Flag, in lowerXALUO()
4367 Flag = DAG.getNode(ISD::AssertZext, DL, MVT::i128, Flag, in lowerUADDSUBO_CARRY()
4716 SDValue OrigVal = DAG.getNode(ISD::AssertZext, DL, WideVT, AtomicOp.getValue(0), in lowerATOMIC_CMP_SWAP()
7022 else if (LHS->getOpcode() == ISD::AssertZext) in combineSTORE()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 665 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1488 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1442 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 1812 case ISD::AssertZext: { in getValueBits()
3202 (Input.getOperand(0).getOpcode() == ISD::AssertZext || in zeroExtendInputIfNeeded()
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