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Searched refs:AfterLegalizeVectorOps (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDAGCombine.h18 AfterLegalizeVectorOps, enumerator
H A DTargetLowering.h4093 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } in isBeforeLegalizeOps()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp813 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in LowerSELECT_CC()
H A DSIISelLowering.cpp6859 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in lowerEXTRACT_VECTOR_ELT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1819 LegalOperations = Level >= AfterLegalizeVectorOps; in Run()
4417 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) { in visitMUL()
14819 if (Level == AfterLegalizeVectorOps && VT.isVector() && in visitTRUNCATE()
22038 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
22528 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) in reduceBuildVecExtToExtBuildVec()
23942 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) { in visitCONCAT_VECTORS()
25542 Level < AfterLegalizeVectorOps && in visitVECTOR_SHUFFLE()
25578 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT) && in visitVECTOR_SHUFFLE()
25702 N1.isUndef() && Level < AfterLegalizeVectorOps && in visitVECTOR_SHUFFLE()
H A DSelectionDAGISel.cpp922 CurDAG->Combine(AfterLegalizeVectorOps, AA, OptLevel); in CodeGenAndEmitDAG()