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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td261 // Boolean vectors of AVX-512 are returned in SIMD registers.
262 // The call from AVX to AVX-512 function should work,
279 // supported while using the AVX target feature.
285 // supported while using the AVX-512 target feature.
581 // Boolean vectors of AVX-512 are passed in SIMD registers.
582 // The call from AVX to AVX-512 function should work,
724 // AVX
728 // AVX-512
799 // AVX 256-bit vector arguments are passed in YMM registers.
863 // Boolean vectors of AVX-512 are passed in SIMD registers.
[all …]
H A DX86.td110 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
111 "Enable AVX instructions",
137 "Enable AVX-512 PreFetch Instructions",
152 "Enable AVX-512 Vector Length eXtensions",
161 "Enable AVX-IFMA",
178 "Enable AVX-512 Bit Algorithms",
194 "Enable AVX-VNNI-INT8",
198 "Enable AVX-VNNI-INT16",
681 // similar to Skylake Server (AVX-512).
695 "Prefer 128-bit AVX instructions">;
[all …]
H A DX86InstrUtils.td490 // AVX instructions have a 'v' prefix in the mnemonic
507 // AVX instructions have a 'v' prefix in the mnemonic
521 // AVX instructions have a 'v' prefix in the mnemonic
536 // AVX instructions have a 'v' prefix in the mnemonic
559 // AVX instructions have a 'v' prefix in the mnemonic
570 // VSSI - SSE1 instructions with XS prefix in AVX form.
689 // classes. They need to be enabled even if AVX is enabled.
736 // AVX Instruction Templates:
739 // AVX8I - AVX instructions with T8, PD prefix.
765 // AVX-512 Instruction Templates:
[all …]
H A DX86Subtarget.h55 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 enumerator
206 bool hasAVX() const { return X86SSELevel >= AVX; } in hasAVX()
H A DX86RegisterInfo.td362 // XMM16-31 registers, used by AVX-512 instructions.
381 // YMM0-15 registers, used by AVX instructions and
382 // YMM16-31 registers, used by AVX-512 instructions.
397 // ZMM Registers, used by AVX-512 instructions.
406 // Mask Registers, used by AVX-512 instructions.
790 // AVX-512 vector/mask registers.
798 // Scalar AVX-512 floating point registers.
805 // Extended VR128 and VR256 for AVX-512 instructions
H A DX86InstrOperands.td388 // Unsigned immediate used by SSE/AVX instructions
427 // Unsigned 8-bit immediate used by SSE/AVX instructions.
443 // Used by some SSE/AVX instructions that use intrinsics.
H A DX86ScheduleBtVer2.td25 // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
806 // AVX instructions.
834 // SSE2/AVX Store Selected Bytes of Double Quadword - (V)MASKMOVDQ
996 // AVX Zero-idioms.
1029 // AVX
1048 // AVX variants.
H A DX86ReplaceableInstrs.def47 // AVX 128-bit support
79 // AVX 256-bit support
H A DX86ScheduleZnver3.td1461 // AVX variants.
1469 // AVX YMM variants.
1569 // AVX XMM Zero-idioms.
1584 // AVX YMM Zero-idioms.
1619 // AVX XMM
1624 // AVX YMM
H A DX86ScheduleZnver1.td1348 // AVX XMM Zero-idioms.
1359 // AVX YMM Zero-idioms.
1386 // AVX XMM
1391 // AVX YMM
H A DX86ScheduleZnver2.td1354 // AVX XMM Zero-idioms.
1365 // AVX YMM Zero-idioms.
1392 // AVX XMM
1397 // AVX YMM
/freebsd-14.2/sys/contrib/openzfs/lib/libspl/include/sys/
H A Dsimd.h88 AVX, enumerator
142 [AVX] = {1U, 0U, 1U << 28, ECX },
215 CPUID_FEATURE_CHECK(avx, AVX);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Support/BLAKE3/
H A Dblake3_dispatch.c68 AVX = 1 << 3, enumerator
114 features |= AVX; in get_cpu_features()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DVFABIDemangler.h48 AVX, // x86 AVX enumerator
/freebsd-14.2/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod58 =item bit #60 denoting AVX extension;
123 C<:~0x20> would disable AVX2 code paths, and C<:0> - all post-AVX
/freebsd-14.2/sys/contrib/libsodium/
H A Dconfigure.ac435 AC_MSG_CHECKING(for AVX instructions set)
438 # error NativeClient detected - Avoiding AVX opcodes
444 AC_DEFINE([HAVE_AVXINTRIN_H], [1], [AVX is available])
632 AC_MSG_CHECKING(whether we can assemble AVX opcodes)
646 AC_DEFINE([HAVE_AVX_ASM], [1], [AVX opcodes are supported])
H A DChangeLog70 AVX* when temperature/power consumption is a concern.
207 - Handle the case where the CPU supports AVX, but we are running
208 on an hypervisor with AVX disabled/not supported.
217 merged in, and is automatically used on CPUs supporting the AVX
/freebsd-14.2/sys/contrib/openzfs/config/
H A Dtoolchain-simd.m4153 AC_MSG_CHECKING([whether host toolchain supports AVX])
163 AC_DEFINE([HAVE_AVX], 1, [Define if host toolchain supports AVX])
/freebsd-14.2/sys/contrib/openzfs/module/icp/asm-x86_64/modes/
H A Dghash-x86_64.S71 # Broadwell 0.45(+110%)(if system doesn't support AVX)
75 # Knights L 2.12(-) (if system doesn't support AVX)
80 # ... 8x aggregate factor AVX code path is using reduction algorithm
81 # suggested by Shay Gueron[1]. Even though contemporary AVX-capable
/freebsd-14.2/contrib/llvm-project/clang/lib/Basic/Targets/
H A DX86.cpp451 .Case("+avx", AVX) in handleTargetFeatures()
966 case AVX: in getTargetDefines()
997 case AVX: in getTargetDefines()
1170 .Case("avx", SSELevel >= AVX) in hasFeature()
H A DX86.h66 AVX, enumerator
343 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) in getABI()
/freebsd-14.2/sys/contrib/xen/arch-x86/
H A Dcpufeatureset.h150 XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */
/freebsd-14.2/sys/contrib/libb2/
H A Dblake2-dispatch.c30 AVX = 4, enumerator
126 feature = AVX; in get_cpu_features()
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DTargetInfo.h535 AVX, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DX86TargetParser.def147 X86_FEATURE_COMPAT(AVX, "avx", 12)

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