Home
last modified time | relevance | path

Searched refs:AVL (Results 1 – 17 of 17) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPISelLowering.cpp24 SDValue AVL = in splitMaskArithmetic() local
63 SDValue AVL; in lowerToVVP() local
77 if (!AVL) in lowerToVVP()
132 SDValue AVL = getNodeAVL(Op); in lowerVVP_LOAD_STORE() local
144 if (!AVL) in lowerVVP_LOAD_STORE()
214 UpperPartAVL = SplitTM.AVL; in splitPackedLoadStore()
238 OpVec.push_back(SplitTM.AVL); in splitPackedLoadStore()
290 if (!AVL) in lowerVVP_GATHER_SCATTER()
410 auto AVL = getNodeAVL(Op); in legalizePackedAVL() local
411 if (isLegalAVL(AVL)) in legalizePackedAVL()
[all …]
H A DVECustomDAG.cpp214 bool isLegalAVL(SDValue AVL) { return AVL->getOpcode() == VEISD::LEGALAVL; } in isLegalAVL() argument
396 SDValue AVL = getNodeAVL(Op); in getAnnotatedNodeAVL() local
397 if (!AVL) in getAnnotatedNodeAVL()
399 if (isLegalAVL(AVL)) in getAnnotatedNodeAVL()
400 return {AVL->getOperand(0), true}; in getAnnotatedNodeAVL()
401 return {AVL, false}; in getAnnotatedNodeAVL()
475 if (isLegalAVL(AVL)) in annotateLegalAVL()
476 return AVL; in annotateLegalAVL()
477 return getNode(VEISD::LEGALAVL, AVL.getValueType(), AVL); in annotateLegalAVL()
487 return DAG.getNode(OC, DL, DestVT, Vec, AVL); in getUnpack()
[all …]
H A DVECustomDAG.h77 bool isLegalAVL(SDValue AVL);
137 SDValue AVL; member
138 VETargetMasks(SDValue Mask = SDValue(), SDValue AVL = SDValue())
139 : Mask(Mask), AVL(AVL) {} in Mask()
185 SDValue VectorV, SDValue Mask, SDValue AVL,
190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const;
191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const;
202 SDValue getMaskBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const;
203 SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const;
206 SDValue annotateLegalAVL(SDValue AVL) const;
[all …]
H A DVEISelLowering.cpp1847 auto AVL = CDAG.getConstant(NumEls, MVT::i32); in lowerBUILD_VECTOR() local
1848 return CDAG.getBroadcast(ResultVT, ScalarV, AVL); in lowerBUILD_VECTOR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td380 fvti.AVL, fvti.Log2SEW)>;
386 fvti.AVL, fvti.Log2SEW)>;
556 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC
572 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC
630 vti.AVL, vti.Log2SEW, TA_MA)>;
674 vti.AVL, vti.Log2SEW,
968 vti.AVL, vti.Log2SEW, TA_MA)>;
973 vti.AVL, vti.Log2SEW, TA_MA)>;
978 vti.AVL, vti.Log2SEW, TA_MA)>;
1127 vti.AVL, vti.Log2SEW)>;
[all …]
H A DRISCVInstrInfoVPseudos.td87 def AVL : RegisterOperand<GPRNoX0> {
93 // rd | rs1 | AVL value | Effect on vl
272 OutPatFrag AVL = VLMax;
400 OutPatFrag AVL = VLMax;
943 AVL:$vl, ixlenimm:$sew), []>,
1297 AVL:$vl, ixlenimm:$sew,
1520 AVL:$vl, ixlenimm:$sew)), []>,
1544 AVL:$vl, ixlenimm:$sew)), []>,
1563 AVL:$vl, ixlenimm:$sew), []>,
1799 AVL:$vl, ixlenimm:$sew), []>,
[all …]
H A DRISCVInstrInfoZvk.td195 (ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
213 AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
422 vti.AVL, vti.Log2SEW, TA_MA)>;
443 vti.AVL, vti.Log2SEW, TA_MA)>;
451 vti.AVL, vti.Log2SEW, TA_MA)>;
492 vti.AVL, vti.Log2SEW, TA_MA)>;
508 vti.AVL, vti.Log2SEW, TA_MA)>;
515 vti.AVL, vti.Log2SEW, TA_MA)>;
522 vti.AVL, vti.Log2SEW, TA_MA)>;
H A DRISCVInstrInfoXSf.td228 AVL:$vl, ixlenimm:$sew), []>,
242 AVL:$vl, ixlenimm:$sew), []>,
256 AVL:$vl, ixlenimm:$sew), []>,
270 AVL:$vl, ixlenimm:$sew), []>,
284 AVL:$vl, ixlenimm:$sew), []>,
298 AVL:$vl, ixlenimm:$sew), []>,
H A DRISCVInsertVSETVLI.cpp1511 auto &AVL = MI.getOperand(1); in canMutatePriorConfig() local
1517 if (AVL.isReg() && AVL.getReg() != RISCV::X0) { in canMutatePriorConfig()
1518 if (AVL.getReg().isPhysical()) in canMutatePriorConfig()
1520 if (!PrevAVL.isReg() || PrevAVL.getReg() != AVL.getReg()) in canMutatePriorConfig()
H A DRISCVISelDAGToDAG.cpp592 uint64_t AVL = C->getZExtValue(); in selectVSETVLI() local
593 if (isUInt<5>(AVL)) { in selectVSETVLI()
594 SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT); in selectVSETVLI()
H A DRISCVISelLowering.cpp8310 SDValue AVL = getVLOperand(Op); in lowerVectorIntrinsicScalars() local
8314 if (isa<ConstantSDNode>(AVL)) { in lowerVectorIntrinsicScalars()
8318 uint64_t AVLInt = AVL->getAsZExtVal(); in lowerVectorIntrinsicScalars()
8346 SDValue VL = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, SETVL, AVL, in lowerVectorIntrinsicScalars()
8391 DAG.getUNDEF(VT), AVL); in lowerVectorIntrinsicScalars()
8395 MaskedOff, AVL); in lowerVectorIntrinsicScalars()
8443 SDValue AVL = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, N->getOperand(1)); in lowerGetVectorLength() local
8447 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, ID, AVL, Sew, LMul); in lowerGetVectorLength()
9171 static bool isNonZeroAVL(SDValue AVL) { in isNonZeroAVL() argument
9172 auto *RegisterAVL = dyn_cast<RegisterSDNode>(AVL); in isNonZeroAVL()
[all …]
/freebsd-14.2/contrib/ncurses/
H A DAUTHORS37 AVL Alexander V Lukyanov
/freebsd-14.2/sys/contrib/edk2/Include/Library/
H A DBaseLib.h5362 UINT32 AVL:1; member
5460 UINT32 AVL:1; ///< Available for use by system software member
5517 UINT32 AVL:1; ///< Available for use by system software member
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td132 /* AVL */ [LLVMMatchType<0>,
/freebsd-14.2/contrib/one-true-awk/testdir/
H A Dfunstack.ok1126 Retrieval Using AVL Trees . . . . . . . 843--843
1499 Caxton C. Foster A Generalization of AVL Trees . . . . . 513--517
H A Dfunstack.in8194 title = "On {Foster}'s Information Storage and Retrieval Using {AVL} Trees",
8208 …keywords = "(mathematical); AVL trees; binary trees; file organisation; information retrieval;…
11203 title = "A Generalization of {AVL} Trees",
11214 …AVL trees is proposed in which imbalances up to (triangle shape) is a small integer. An experiment…
11220 …keywords = "AVL trees; balanced trees; file organisation; generalisation; information retrieva…
17657 …is shown that the only statistic of HB left bracket 1 right bracket trees (AVL trees) that is a fu…
20373 …AVL and extensions), weight-balance (i.e. BB and WB), and total restructuring-for building balance…
20380 …keywords = "analysis of algorithms; AVL trees; binary search trees; computer programming --- S…
22579 …keywords = "AVL trees; balanced trees; binary search; computer programming; dynamic balancing",
23144 …AVL tree in that only one bit of balancing information is required (two bits are required for the …
[all …]
/freebsd-14.2/share/misc/
H A Dusb_vendors1341 0961 AVL Flash Card Reader