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Searched refs:AVGCEILS (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h662 AVGCEILS, enumerator
H A DTargetLowering.h2797 case ISD::AVGCEILS: in isCommutativeBinOp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp244 case ISD::AVGCEILS: return "avgceils"; in getOperationName()
H A DLegalizeVectorTypes.cpp4153 case ISD::AVGCEILS: in WidenVectorResult()
H A DSelectionDAG.cpp5970 case ISD::AVGCEILS: { in FoldValue()
H A DTargetLowering.cpp1039 unsigned AVGOpc = IsCeil ? (IsSigned ? ISD::AVGCEILS : ISD::AVGCEILU) in combineShiftToAVG()
H A DDAGCombiner.cpp1956 case ISD::AVGCEILS: in visit()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp865 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td395 def avgceils : SDNode<"ISD::AVGCEILS" , SDTIntBinOp, [SDNPCommutative]>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1177 setOperationAction(ISD::AVGCEILS, VT, Legal); in AArch64TargetLowering()
1356 setOperationAction(ISD::AVGCEILS, VT, Custom); in AArch64TargetLowering()
5449 ? (IsRoundingAdd ? ISD::AVGCEILS : ISD::AVGFLOORS) in LowerINTRINSIC_WO_CHAIN()
6368 case ISD::AVGCEILS: in LowerOperation()
14412 (Op->getOpcode() == ISD::AVGCEILS || Op->getOpcode() == ISD::AVGCEILU); in LowerAVG()
14414 (Op->getOpcode() == ISD::AVGFLOORS || Op->getOpcode() == ISD::AVGCEILS); in LowerAVG()
18239 (N0Opc == ISD::AVGCEILU || N0Opc == ISD::AVGCEILS || in performConcatVectorsCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp279 setOperationAction(ISD::AVGCEILS, VT, Legal); in addMVEVectorTypes()