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Searched refs:ARC (Results 1 – 25 of 98) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp66 AdjOp = Positive ? ARC::ADD_rru6 : ARC::SUB_rru6; in generateStackAdjustment()
68 AdjOp = Positive ? ARC::ADD_rrs12 : ARC::SUB_rrs12; in generateStackAdjustment()
70 AdjOp = Positive ? ARC::ADD_rrlimm : ARC::SUB_rrlimm; in generateStackAdjustment()
80 assert(Reg.getReg() >= ARC::R13 && Reg.getReg() <= ARC::R25 && in determineLastCalleeSave()
143 .addReg(ARC::SP) in emitPrologue()
150 .addReg(ARC::FP) in emitPrologue()
151 .addReg(ARC::SP) in emitPrologue()
189 ARC::FP) in emitPrologue()
456 Opc = IsAdd ? ARC::ADD_rru6 : ARC::SUB_rru6; in emitRegUpdate()
458 Opc = IsAdd ? ARC::ADD_rrs12 : ARC::SUB_rrs12; in emitRegUpdate()
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H A DARCRegisterInfo.cpp75 unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; in replaceFrameIndex()
84 case ARC::LD_rs9: in replaceFrameIndex()
87 case ARC::LDH_rs9: in replaceFrameIndex()
88 case ARC::LDH_X_rs9: in replaceFrameIndex()
91 case ARC::LDB_rs9: in replaceFrameIndex()
99 case ARC::ST_rs9: in replaceFrameIndex()
102 case ARC::STH_rs9: in replaceFrameIndex()
105 case ARC::STB_rs9: in replaceFrameIndex()
113 case ARC::GETFI: in replaceFrameIndex()
116 TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm)) in replaceFrameIndex()
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H A DARCExpandPseudos.cpp51 case ARC::ST_FAR: in getMappedOp()
52 return ARC::ST_rs9; in getMappedOp()
53 case ARC::STH_FAR: in getMappedOp()
54 return ARC::STH_rs9; in getMappedOp()
55 case ARC::STB_FAR: in getMappedOp()
56 return ARC::STB_rs9; in getMappedOp()
67 isUInt<6>(SI.getOperand(2).getImm()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; in expandStore()
140 case ARC::ST_FAR: in runOnMachineFunction()
141 case ARC::STH_FAR: in runOnMachineFunction()
146 case ARC::CTLZ: in runOnMachineFunction()
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H A DARCInstrInfo.cpp47 : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {} in ARCInstrInfo()
54 return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 || in isLoad()
55 Opcode == ARC::LDB_rs9; in isLoad()
59 return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 || in isStore()
60 Opcode == ARC::STB_rs9; in isStore()
140 return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p; in isCondBranchOpcode()
285 assert(ARC::GPR32RegClass.contains(SrcReg) && in copyPhysReg()
313 BuildMI(MBB, I, DL, get(ARC::ST_rs9)) in storeRegToStackSlot()
341 BuildMI(MBB, I, DL, get(ARC::LD_rs9)) in loadRegFromStackSlot()
385 int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p; in insertBranch()
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H A DARCBranchFinalize.cpp96 return !(MI->getOpcode() != ARC::BRcc_rr_p && in isBRccPseudo()
97 MI->getOpcode() != ARC::BRcc_ru6_p); in isBRccPseudo()
102 if (MI->getOpcode() == ARC::BRcc_rr_p) in getBRccForPseudo()
103 return ARC::BRcc_rr; in getBRccForPseudo()
104 return ARC::BRcc_ru6; in getBRccForPseudo()
109 if (MI->getOpcode() == ARC::BRcc_rr_p) in getCmpForPseudo()
110 return ARC::CMP_rr; in getCmpForPseudo()
111 return ARC::CMP_ru6; in getCmpForPseudo()
137 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc)) in replaceWithCmpBcc()
H A DARCRegisterInfo.td1 //===- ARCRegisterInfo.td - ARC Register defs --------------*- tablegen -*-===//
10 // Declarations that describe the ARC register file
15 let Namespace = "ARC";
60 def STATUS32 : Aux<10, "status32">; // No DwarfRegNum defined in the ARC ABI
63 def GPR32: RegisterClass<"ARC", [i32], 32,
75 def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>;
77 def GPR_S : RegisterClass<"ARC", [i32], 8,
H A DARC.td1 //===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===//
12 // ARC Subtarget features
34 def ARC : Target {
H A DARCCallingConv.td1 //===- ARCCallingConv.td - Calling Conventions for ARC -----*- tablegen -*-===//
8 // This describes the calling conventions for ARC architecture.
12 // ARC Return Value Calling Convention
25 // ARC Argument Calling Conventions
H A DARCISelLowering.cpp100 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
105 setStackPointerRegisterToSaveRestore(ARC::SP); in ARCTargetLowering()
329 StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP, in LowerCall()
438 SDValue StackPtr = DAG.getRegister(ARC::SP, MVT::i32); in lowerCallResult()
531 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
559 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments()
560 ARC::R4, ARC::R5, ARC::R6, ARC::R7}; in LowerCallArguments()
575 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
H A DARCOptAddrMode.cpp137 case ARC::SUB_rru6: in isAddConstantOp()
140 case ARC::ADD_rru6: in isAddConstantOp()
263 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine()
485 if (ARC::getPostIncOpcode(MI->getOpcode()) < 0) in processBasicBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp125 ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
126 ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
127 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
128 ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
129 ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};
/freebsd-14.2/sys/contrib/device-tree/Bindings/timer/
H A Dsnps,arc-timer.txt1 Synopsys ARC Local Timer with Interrupt Capabilities
2 - Found on all ARC CPUs (ARC700/ARCHS)
4 - Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
6 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
H A Dsnps,archs-rtc.txt1 Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
H A Dsnps,archs-gfrc.txt1 Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
/freebsd-14.2/sys/contrib/device-tree/Bindings/arc/
H A Dhsdk.txt1 Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
4 ARC HSDK Board with quad-core ARC HS38x4 in silicon.
H A Darchs-pct.txt1 * ARC HS Performance Counters
3 The ARC HS can be configured with a pipeline performance monitor for counting
H A Dpct.txt1 * ARC Performance Counters
8 * The ARC 700 PCT does not support interrupts; although HW events may be
H A Daxs101.txt1 Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
/freebsd-14.2/sys/contrib/device-tree/Bindings/remoteproc/
H A Damlogic,meson-mx-ao-arc.yaml7 title: Amlogic Meson AO ARC Remote Processor
10 Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC core
12 system suspend. Meson6 and older use a ARC core based on the ARCv1
13 ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA)
54 the ARC core. The region should be defined as child nodes of the
/freebsd-14.2/sys/contrib/device-tree/Bindings/display/
H A Dsnps,arcpgu.txt1 ARC PGU
4 by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
12 - clock-names: A list of clock names. For ARC PGU it should contain:
/freebsd-14.2/sys/contrib/device-tree/Bindings/serio/
H A Dsnps-arc_ps2.txt1 * ARC PS/2 driver: PS/2 block used in some ARC FPGA's & nSIM OSCI model
/freebsd-14.2/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsnps,archs-intc.txt1 * ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
12 intc accessed via the special ARC AUX register interface, hence "reg" property
H A Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
26 The interrupt controller is accessed via the special ARC AUX register
/freebsd-14.2/sys/contrib/device-tree/Bindings/serial/
H A Darc-uart.txt1 * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCMCTargetDesc.cpp46 InitARCMCRegisterInfo(X, ARC::BLINK); in createARCMCRegisterInfo()
61 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, ARC::SP, 0); in createARCMCAsmInfo()

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