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Searched refs:ALU (Results 1 – 25 of 75) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSchedule.td12 def ALU : FuncUnit;
389 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
390 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
391 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
392 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
393 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
394 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
395 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
396 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
397 InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td786 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
795 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
814 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
826 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
836 // Requires consecutive Load and ALU pieces totaling 7 cycles. The Load and ALU
859 // Requires consecutive Load and ALU pieces totaling 8 cycles. The Load and ALU
984 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
993 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
1009 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
1049 // One is three cycle ALU the ohter is a two cycle ALU.
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H A DP10InstrResources.td864 // 2 Cycles ALU operations, 1 input operands
871 // 3 Cycles ALU operations, 0 input operands
881 // 3 Cycles ALU operations, 1 input operands
966 // 3 Cycles ALU operations, 2 input operands
1109 // 3 Cycles ALU operations, 3 input operands
1120 // 3 Cycles ALU operations, 0 input operands
1172 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands
1187 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands
1199 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands
1212 // 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU oper…
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H A DPPCScheduleP9.td88 // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
89 def ALU : ProcResource<4>;
91 //Even ALU pipelines
92 let Super = ALU;
95 //Odd ALU pipelines
96 let Super = ALU;
190 // ALU Units
191 // An ALU may take either 2 or 3 cycles to complete the operation.
192 // However, the ALU unit is only ever busy for 1 cycle at a time and may
194 def P9_ALU_2C : SchedWriteRes<[ALU]> {
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600Schedule.td10 // slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
H A DR600Processors.td19 "Older version of ALU instructions encoding"
H A DAMDGPUIGroupLP.cpp68 ALU = 1u << 0, enumerator
79 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
1438 else if (((SGMask & SchedGroupMask::ALU) != SchedGroupMask::NONE) && in canAddMI()
1665 if ((InvertedMask & SchedGroupMask::ALU) == SchedGroupMask::NONE) in invertSchedBarrierMask()
1673 InvertedMask &= ~SchedGroupMask::ALU; in invertSchedBarrierMask()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td24 def WriteI : SchedWrite; // ALU
25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
26 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
27 def ReadI : SchedRead; // ALU
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg
H A DAArch64SchedA55.td44 def CortexA55UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
51 // The FP DIV/SQRT instructions execute totally differently from the FP ALU
54 def CortexA55UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU
67 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
68 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
69 def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg
147 // FP ALU
181 // FP ALU specific new schedwrite definitions
215 // ALU - ALU input operands are generally needed in EX1. An operand produced in
216 // in say EX2 can be forwarded for consumption to ALU in EX1, thereby
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H A DAArch64SchedA53.td42 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
47 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
57 // ALU - Despite having a full latency of 4, most of the ALU instructions can
125 // FP ALU
157 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
H A DAArch64SchedThunderX.td37 def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
42 def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
51 // ALU
152 // FP ALU
200 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
H A DAArch64SchedTSV110.td37 def TSV110UnitALU : ProcResource<1>; // Int ALU
38 def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU
55 // Integer ALU
56 // TODO: Use SchedVariant to select BRU for ALU ops that sets NZCV flags
135 // MicroOp Count/Types: #(ALU|AB|MDU|FSU1|FSU2|LdSt|ALUAB|F|FLdSt)
138 // 1 micro-ops to be issued down one ALU pipe, six MDU pipes and four LdSt pipes.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td54 def ALU : ProcResource<1> { let BufferSize = 0; }
68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td272 // ALU instructions
322 defm ADD : ALU<BPF_ADD, 0, "+=", add>;
323 defm SUB : ALU<BPF_SUB, 0, "-=", sub>;
324 defm OR : ALU<BPF_OR, 0, "|=", or>;
325 defm AND : ALU<BPF_AND, 0, "&=", and>;
326 defm SLL : ALU<BPF_LSH, 0, "<<=", shl>;
327 defm SRL : ALU<BPF_RSH, 0, ">>=", srl>;
328 defm XOR : ALU<BPF_XOR, 0, "^=", xor>;
331 defm MUL : ALU<BPF_MUL, 0, "*=", mul>;
332 defm DIV : ALU<BPF_DIV, 0, "/=", udiv>;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td25 // The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
35 // for scheduling, so simple ALU operations executing in EX2 will have
58 // Basic ALU with shifts.
117 // ALU operations (32/64-bit). These go down the FP pipeline.
188 // Assume that these will go down the main ALU pipeline.
319 // Sched definitions for ALU
322 // Shifted ALU operands are read a cycle early.
H A DARMSchedule.td44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
59 // Basic ALU operation.
63 // Basic ALU with shifts.
111 // ALU operations (32/64-bit)
H A DARMScheduleV6.td227 // Single-precision FP ALU
230 // Double-precision FP ALU
H A DARMScheduleM85.td35 // CortexM85 has two ALU, two LOAD, two STORE, a MAC, a BRANCH and two VFP
74 // Basic ALU with shifts.
132 // ALU operations (32/64-bit). These go down the FP pipeline.
204 // Assume that these will go down the main ALU pipeline.
392 // Sched definitions for ALU
395 // Non-small shifted ALU operands are read a cycle early; small LSLs
H A DARMScheduleM55.td106 def M55UnitALU : ProcResource<1> { let BufferSize = 0; } // Int ALU
123 // ALU //
131 // DX instructions are ALU instructions that take a single cycle. The
238 // No forwarding in the ALU normally
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td222 // ALU32/ALU
225 // ALU32 / ALU / Logical Operations.
272 // XTYPE/ALU
281 // XTYPE / ALU / Logical-logical Words.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
129 def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I
H A DRISCVSchedRocket.td33 def RocketUnitALU : ProcResource<1>; // Int ALU
38 def RocketUnitFPALU : ProcResource<1>; // FP ALU
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Schedule.td134 defm WriteALU : X86SchedWritePair; // Simple integer ALU op.
135 defm WriteADC : X86SchedWritePair; // Integer ALU + flags op.
361 defm WriteVecALU : X86SchedWritePair<ReadAfterVecLd>; // Vector integer ALU op, no logicals.
362 defm WriteVecALUX : X86SchedWritePair<ReadAfterVecXLd>; // Vector integer ALU op, no logicals (XM…
363 defm WriteVecALUY : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (YM…
364 defm WriteVecALUZ : X86SchedWritePair<ReadAfterVecYLd>; // Vector integer ALU op, no logicals (ZM…
H A DX86ScheduleAtom.td35 def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store
36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
37 def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA
38 // SIMD/FP: SIMD ALU, FP Adder
203 // to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
H A DX86ScheduleZnver3.td92 // each one servicing one ALU pipeline and one or two other pipelines
100 // Each pipe has an ALU capable of general purpose integer operations.
136 // General ALU operations
531 defm : Zn3WriteResIntPair<WriteALU, [Zn3ALU0123], 1, [1], 1>; // Simple integer ALU op.
566 defm : Zn3WriteResIntPair<WriteADC, [Zn3ALU0123], 1, [4], 1>; // Integer ALU + flags op.
1036 defm : Zn3WriteResXMMPair<WriteVecALU, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no l…
1052 defm : Zn3WriteResXMMPair<WriteVecALUX, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no l…
1081 defm : Zn3WriteResYMMPair<WriteVecALUY, [Zn3FPVAdd0123], 1, [1], 1>; // Vector integer ALU op, no l…
1095 defm : X86WriteResPairUnsupported<WriteVecALUZ>; // Vector integer ALU op, no logicals (ZMM).

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