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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMacroFusion.td12 // Fuse LUI followed by ADDI or ADDIW:
18 "Enable LUI+ADDI macro fusion",
20 CheckOpcode<[ADDI, ADDIW]>>;
22 // Fuse AUIPC followed by ADDI:
27 "Enable AUIPC+ADDI macrofusion",
29 CheckOpcode<[ADDI]>>;
H A DRISCVMergeBaseOffset.cpp105 if (Lo->getOpcode() != RISCV::ADDI) in INITIALIZE_PASS()
188 if (OffsetTail.getOpcode() == RISCV::ADDI || in foldLargeOffset()
269 if (OffsetTail.getOpcode() != RISCV::ADDI) in foldShiftedOffset()
312 case RISCV::ADDI: { in detectAndFoldOffset()
320 if (TailTail.getOpcode() == RISCV::ADDI) { in detectAndFoldOffset()
H A DRISCVRegisterInfo.cpp233 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
251 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
255 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
463 if (MI.getOpcode() == RISCV::ADDI && !isInt<12>(Offset.getFixed())) { in eliminateFrameIndex()
491 if (MI.getOpcode() == RISCV::ADDI) in eliminateFrameIndex()
507 if (MI.getOpcode() == RISCV::ADDI && in eliminateFrameIndex()
635 BuildMI(*MBB, MBBI, DL, TII->get(RISCV::ADDI), BaseReg) in materializeFrameBaseRegister()
810 case RISCV::ADDI: in getRegAllocationHints()
H A DRISCVOptWInstrs.cpp286 case RISCV::ADDI: in hasAllNBitUsers()
356 case RISCV::ADDI: in isSignExtendingOpW()
582 case RISCV::ADDI: in isSignExtendedW()
603 case RISCV::ADDI: in getWOp()
688 case RISCV::ADDIW: Opc = RISCV::ADDI; break; in stripWSuffixes()
H A DRISCVAsmPrinter.cpp500 EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::ADDI) in LowerKCFI_CHECK()
535 : RISCV::ADDI) in LowerKCFI_CHECK()
636 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
654 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
716 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
746 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
752 MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
H A DRISCVGISel.td87 (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm))>;
116 (SLTIU (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm12)), 1)>;
121 (SLTU (XLenVT X0), (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm12)))>;
H A DRISCVExpandPseudoInsts.cpp201 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg) in expandCCOp()
217 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break; in expandCCOp()
531 RISCV::ADDI); in expandLoadLocalAddress()
554 RISCV::ADDI); in expandLoadTLSGDAddress()
585 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10) in expandLoadTLSDescAddress()
H A DRISCVInstrInfo.td423 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
644 def ADDI : ALU_ri<0b000, "addi">;
1236 def : PatGprSimm12<add, ADDI>;
1255 def : PatGprSimm12<or_is_add, ADDI>;
1299 (ADDI GPR:$rs1, simm12:$imm12)>;
1309 (ADDI GPR:$hi, tglobaladdr:$lo)>;
1311 (ADDI GPR:$hi, tblockaddress:$lo)>;
1313 (ADDI GPR:$hi, tjumptable:$lo)>;
1315 (ADDI GPR:$hi, tconstpool:$lo)>;
1323 (ADDI GPR:$src, tglobaltlsaddr:$lo)>;
[all …]
H A DRISCVInstrInfo.cpp76 return MCInstBuilder(RISCV::ADDI) in getNop()
411 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in copyPhysReg()
419 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), in copyPhysReg()
424 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), in copyPhysReg()
1203 if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() && in optimizeCondBranch()
1333 case RISCV::ADDI: return RISCV::PseudoCCADDI; break; in getPredicatedOpcode()
1376 if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() && in canFoldAsPredicatedOp()
1567 case RISCV::ADDI: in isAsCheapAsAMove()
1584 case RISCV::ADDI: in isCopyInstrImpl()
2554 if (MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() && in isAddImmediate()
[all …]
H A DRISCVInstrInfoC.td848 def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
894 def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
895 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
910 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
912 def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
1004 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
H A DRISCVFrameLowering.cpp77 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSPrologue()
137 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSEpilogue()
690 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg) in emitPrologue()
1120 } else if (MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) { in getScavSlotsNumForRVV()
H A DRISCVMakeCompressible.cpp351 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::ADDI), NewReg) in runOnMachineFunction()
H A DRISCVExpandAtomicPseudoInsts.cpp352 BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg) in doMaskedAtomicBinOpExpansion()
492 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg) in expandAtomicMinMaxOp()
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h166 return ADDI{rd, Rs{0}, uint32_t(imm)}; in DecodeC_LI()
167 return ADDI{rd, Rs{0}, uint32_t(int32_t(int8_t(imm | 0xc0)))}; in DecodeC_LI()
183 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, uint32_t(nzimm)}; in DecodeC_LUI_ADDI16SP()
184 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, in DecodeC_LUI_ADDI16SP()
200 return ADDI{rd, rd, uint32_t(imm)}; in DecodeC_ADDI()
201 return ADDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))}; in DecodeC_ADDI()
225 return ADDI{rd, Rs{gpr_sp_riscv}, uint32_t(nzuimm)}; in DecodeC_ADDI4SPN()
H A DRISCVInstructions.h121 I_TYPE_INST(ADDI);
276 LUI, AUIPC, JAL, JALR, B, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp28 case RISCV::ADDI: in getInstSeqCost()
74 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
152 Res.emplace_back(RISCV::ADDI, Lo12); in generateInstSeqImpl()
271 TmpSeq.emplace_back(RISCV::ADDI, Imm12); in generateInstSeq()
413 TmpSeq.emplace_back(RISCV::ADDI, Lo12); in generateInstSeq()
428 TmpSeq.emplace_back(RISCV::ADDI, NegImm12); in generateInstSeq()
503 case RISCV::ADDI: in getOpndKind()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def35 FUSION_OP_SET(ADDI, ADDI8, ADDItocL), \
138 FUSION_OP_SET(ADDI, ADDI8, ADDItocL))
142 FUSION_OP_SET(ADDI, ADDI8, ADDItocL),
H A DPPCBack2BackFusion.def21 ADDI,
510 ADDI,
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
H A DPPCCTRLoops.cpp250 unsigned ADDIOpcode = Is64Bit ? PPC::ADDI8 : PPC::ADDI; in expandNormalLoops()
H A DPPCRegisterInfo.cpp110 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
779 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
832 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) in prepareDynamicAlloca()
1872 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && in needsFrameBaseReg()
1902 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; in materializeFrameBaseRegister()
H A DPPCExpandISEL.cpp447 TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI)) in populateBlocks()
/freebsd-14.2/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp62 ADDI = 0x13, enumerator
238 write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12)); in writePltHeader()
239 write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset))); in writePltHeader()
255 write32le(buf + 12, itype(ADDI, 0, 0, 0)); in writePlt()
584 write32le(loc, itype(ADDI, X_A0, 0, val)); // addi a0,zero,<lo12> in tlsdescToLe()
586 write32le(loc, itype(ADDI, X_A0, X_A0, lo12(val))); // addi a0,a0,<lo12> in tlsdescToLe()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp872 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressPcrel() local
877 LoongArchAsmParser::Inst(ADDI, LoongArchMCExpr::VK_LoongArch_PCALA_LO12)); in emitLoadAddressPcrel()
1028 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressTLSLD() local
1033 ADDI, LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12)); in emitLoadAddressTLSLD()
1074 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressTLSGD() local
1079 ADDI, LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12)); in emitLoadAddressTLSGD()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp433 MachineInstr &ADDI = in insertIndirectBranch() local
461 ADDI.getOperand(2).setMBB(&RestoreBB); in insertIndirectBranch()

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