| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCBack2BackFusion.def | 15 ADDE,
504 ADDE,
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| H A D | PPCScheduleP7.td | 188 ADDE, ADDE8, ADDME, ADDME8, SUBFME, SUBFME8,
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| H A D | P10InstrResources.td | 971 ADDE, ADDE8,
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| H A D | PPCISelLowering.cpp | 244 setOperationAction(ISD::ADDE, VT, Legal); in PPCTargetLowering()
17689 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
17704 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 279 ADDE, enumerator
|
| H A D | TargetLowering.h | 2786 case ISD::ADDE: in isCommutativeBinOp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelDAGToDAG.cpp | 222 case ISD::ADDE: in isdToLanaiAluCode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 220 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"); in selectAddE()
762 case ISD::ADDE: { in trySelect()
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| H A D | MipsSEISelLowering.cpp | 106 setOperationAction(ISD::ADDE, MVT::i32, Legal); in MipsSETargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1737 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1743 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
3139 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
3140 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3295 case ISD::ADDE: in LowerOperation()
|
| H A D | SparcInstrInfo.td | 826 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 110 ADDE, // Add using carry enumerator
|
| H A D | ARMISelLowering.cpp | 1730 MAKE_CASE(ARMISD::ADDE) in getTargetNodeName()
5020 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), in ConvertCarryFlagToBooleanCarry()
9882 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0), in LowerUADDSUBO_CARRY()
12910 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE || in AddCombineTo64bitMLAL()
12920 if ((AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
12939 if (AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
13118 (AddeNode->getOpcode() == ARMISD::ADDE) && in PerformUMLALCombine()
13139 if (LHS->getOpcode() == ARMISD::ADDE && in PerformAddcSubcCombine()
18866 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget); in PerformDAGCombine()
20063 case ARMISD::ADDE: in computeKnownBitsForTargetNode()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 317 case ISD::ADDE: return "adde"; in getOperationName()
|
| H A D | LegalizeIntegerTypes.cpp | 207 case ISD::ADDE: in PromoteIntegerResult()
2715 case ISD::ADDE: in ExpandIntegerResult()
3242 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
3350 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
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| H A D | SelectionDAG.cpp | 3774 case ISD::ADDE: { in computeKnownBits()
3779 if (Opcode == ISD::ADDE) in computeKnownBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 125 setOperationAction(ISD::ADDE, MVT::i32, Legal); in ARCTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 513 case ISD::ADDE: in Select()
825 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); in SelectADD_SUB_I64()
828 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 188 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 109 setOperationAction(ISD::ADDE, VT, Custom); in M68kTargetLowering()
1397 case ISD::ADDE: in LowerOperation()
2624 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 519 {ISD::ABS, ISD::ADD, ISD::ADDC, ISD::ADDE, in NVPTXTargetLowering()
702 setOperationAction(ISD::ADDE, MVT::i32, Legal); in NVPTXTargetLowering()
707 setOperationAction(ISD::ADDE, MVT::i64, Legal); in NVPTXTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 860 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 74 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 146 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 422 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
|