| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 669 ABDS, enumerator
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| H A D | TargetLowering.h | 2799 case ISD::ABDS: in isCommutativeBinOp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 245 case ISD::ABDS: return "abds"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 962 case ISD::ABDS: in Expand()
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| H A D | DAGCombiner.cpp | 1958 case ISD::ABDS: in visit()
4173 if (SDValue R = MatchSubMaxMin(ISD::SMAX, ISD::SMIN, ISD::ABDS)) in visitSUB()
5291 if (Opcode == ISD::ABDS) in visitABD()
5303 if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) && in visitABD()
10940 if (AbsOp1->getFlags().hasNoSignedWrap() && hasOperation(ISD::ABDS, VT) && in foldABSToABD()
10942 SDValue ABD = DAG.getNode(ISD::ABDS, DL, VT, Op0, Op1); in foldABSToABD()
10956 unsigned ABDOpcode = (Opc0 == ISD::ZERO_EXTEND) ? ISD::ABDU : ISD::ABDS; in foldABSToABD()
12257 unsigned ABDOpc = IsSigned ? ISD::ABDS : ISD::ABDU; in visitVSELECT()
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| H A D | SelectionDAG.cpp | 5982 case ISD::ABDS: in FoldValue()
6663 case ISD::ABDS: in getNode()
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| H A D | LegalizeDAG.cpp | 3004 case ISD::ABDS: in ExpandNode()
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| H A D | TargetLowering.cpp | 9003 bool IsSigned = N->getOpcode() == ISD::ABDS; in expandABD()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 869 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1179 setOperationAction(ISD::ABDS, VT, Legal); in AArch64TargetLowering()
1326 setOperationAction(ISD::ABDS, VT, Custom); in AArch64TargetLowering()
6360 case ISD::ABDS: in LowerOperation()
16567 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
16578 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
20047 return DAG.getNode(ISD::ABDS, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
20168 return DAG.getNode(ISD::ABDS, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
20348 N->getOperand(0).getOpcode() == ISD::ABDS)) { in performExtendCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 397 def abds : SDNode<"ISD::ABDS" , SDTIntBinOp, [SDNPCommutative]>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 191 for (auto Op : {ISD::ABDS, ISD::ABDU}) { in X86TargetLowering()
1067 setOperationAction(ISD::ABDS, MVT::v16i8, Custom); in X86TargetLowering()
1069 setOperationAction(ISD::ABDS, MVT::v8i16, Custom); in X86TargetLowering()
1071 setOperationAction(ISD::ABDS, MVT::v4i32, Custom); in X86TargetLowering()
1288 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
1433 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
1856 setOperationAction(ISD::ABDS, VT, Custom); in X86TargetLowering()
28209 bool IsSigned = Op.getOpcode() == ISD::ABDS; in LowerABD()
31992 case ISD::ABDS: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1321 setOperationAction(ISD::ABDS, MVT::v4i32, Legal); in PPCTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 275 setOperationAction(ISD::ABDS, VT, Legal); in addMVEVectorTypes()
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