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Searched refs:AArch64InstrInfo (Results 1 – 25 of 25) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp29 return AArch64InstrInfo::getLdStOffsetOp(*MI).isImm(); in needReorderStoreMI()
38 const MachineOperand &Base0 = AArch64InstrInfo::getLdStBaseOp(MI0); in mayOverlapWrite()
39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite()
45 int StoreSize0 = AArch64InstrInfo::getMemScale(MI0); in mayOverlapWrite()
46 int StoreSize1 = AArch64InstrInfo::getMemScale(MI1); in mayOverlapWrite()
47 Off0 = AArch64InstrInfo::hasUnscaledLdStOffset(MI0.getOpcode()) in mayOverlapWrite()
48 ? AArch64InstrInfo::getLdStOffsetOp(MI0).getImm() in mayOverlapWrite()
50 Off1 = AArch64InstrInfo::hasUnscaledLdStOffset(MI1.getOpcode()) in mayOverlapWrite()
51 ? AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() in mayOverlapWrite()
55 int Multiples = AArch64InstrInfo::isPairedLdSt(MI) ? 2 : 1; in mayOverlapWrite()
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H A DAArch64LoadStoreOptimizer.cpp124 const AArch64InstrInfo *TII;
599 bool IsPaired = AArch64InstrInfo::isPairedLdSt(MI); in getPrePostIndexedMemOpInfo()
618 bool IsPreLdSt = AArch64InstrInfo::isPreLdSt(MI); in getLdStRegOp()
718 if (!AArch64InstrInfo::getLdStOffsetOp(MI).isImm()) in isMergeableLdStUpdate()
1010 !AArch64InstrInfo::isPreLdSt(*I)) { in mergePairedInsns()
1068 if (AArch64InstrInfo::isPreLdSt(*RtMI)) in mergePairedInsns()
1380 return !AArch64InstrInfo::isPreLdSt(FirstMI); in areCandidatesToMergeOrPair()
1383 if (AArch64InstrInfo::isPreLdSt(FirstMI) && AArch64InstrInfo::isPreLdSt(MI)) in areCandidatesToMergeOrPair()
2004 if (!AArch64InstrInfo::isPairedLdSt(*I)) { in mergeUpdateInsn()
2009 .add(AArch64InstrInfo::getLdStBaseOp(*I)) in mergeUpdateInsn()
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H A DAArch64MacroFusion.cpp64 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticBccPair()
114 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticCbzPair()
251 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isCCSelectPair()
253 return !AArch64InstrInfo::hasExtendedReg(*FirstMI); in isCCSelectPair()
269 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isCCSelectPair()
272 return !AArch64InstrInfo::hasExtendedReg(*FirstMI); in isCCSelectPair()
285 if (AArch64InstrInfo::hasShiftedReg(SecondMI)) in isArithmeticLogicPair()
346 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticLogicPair()
374 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticLogicPair()
414 if (AArch64InstrInfo::hasShiftedReg(*FirstMI)) in isAddSub2RegAndConstOnePair()
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H A DAArch64InstrInfo.cpp80 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI) in AArch64InstrInfo() function in AArch64InstrInfo
573 void AArch64InstrInfo::instantiateCondBranch( in instantiateCondBranch()
590 unsigned AArch64InstrInfo::insertBranch( in insertBranch()
1356 bool AArch64InstrInfo::optimizePTestInstr( in optimizePTestInstr()
1515 bool AArch64InstrInfo::optimizeCompareInstr( in optimizeCompareInstr()
1793 bool AArch64InstrInfo::substituteCmpToZero( in substituteCmpToZero()
4088 AArch64InstrInfo::isPairedLdSt(MI) || AArch64InstrInfo::isPreLdSt(MI) ? 2 in getLdStBaseOp()
4096 AArch64InstrInfo::isPairedLdSt(MI) || AArch64InstrInfo::isPreLdSt(MI) ? 3 in getLdStOffsetOp()
5765 MCInst AArch64InstrInfo::getNop() const { in getNop()
8976 void AArch64InstrInfo::buildOutlinedFrame( in buildOutlinedFrame()
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H A DAArch64BranchTargets.cpp114 const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( in addBTI()
H A DAArch64StorePairSuppress.cpp32 const AArch64InstrInfo *TII;
130 TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
H A DAArch64PointerAuth.cpp41 const AArch64InstrInfo *TII = nullptr;
230 const AArch64InstrInfo *TII = Subtarget.getInstrInfo(); in checkAuthenticatedRegister()
349 assert(AArch64InstrInfo::isTailCallReturnInst(*TI) && in checkAuthenticatedLR()
388 if (AArch64InstrInfo::isTailCallReturnInst(MI)) in runOnMachineFunction()
H A DAArch64Schedule.td13 const AArch64InstrInfo *TII =
14 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
H A DAArch64LowerHomogeneousPrologEpilog.cpp46 const AArch64InstrInfo *TII;
226 AArch64InstrInfo::getMemOpInfo(Opc, Scale, Width, MinOffset, MaxOffset); in emitStore()
267 AArch64InstrInfo::getMemOpInfo(Opc, Scale, Width, MinOffset, MaxOffset); in emitLoad()
661 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64CondBrTuning.cpp48 const AArch64InstrInfo *TII;
289 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64Subtarget.h144 AArch64InstrInfo InstrInfo;
192 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
H A DAArch64StackTaggingPreRA.cpp63 const AArch64InstrInfo *TII;
341 TII = static_cast<const AArch64InstrInfo *>(MF->getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64InstrInfo.h36 class AArch64InstrInfo final : public AArch64GenInstrInfo {
41 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
492 const AArch64InstrInfo *TII);
H A DAArch64SchedPredicates.td78 "AArch64InstrInfo::isFpOrNEON"
84 "AArch64InstrInfo::isHForm"
90 "AArch64InstrInfo::isQForm"
H A DAArch64RegisterInfo.cpp776 const AArch64InstrInfo *TII = in materializeFrameBaseRegister()
804 const AArch64InstrInfo *TII = in resolveFrameIndex()
816 const AArch64InstrInfo *TII) { in createScratchRegisterForInstruction()
876 const AArch64InstrInfo *TII = in eliminateFrameIndex()
H A DAArch64FrameLowering.cpp493 const AArch64InstrInfo *TII = in eliminateCallFramePseudoInstr()
973 const AArch64InstrInfo &TII = *STI.getInstrInfo(); in emitZeroCallUsedRegs()
1388 if (AArch64InstrInfo::isSEHInstruction(*SEH)) in convertCalleeSaveRestoreToSPPrePostIncDec()
1455 if (AArch64InstrInfo::isSEHInstruction(MI)) in fixupCalleeSaveRestoreStackOffset()
1494 assert(AArch64InstrInfo::isSEHInstruction(*MBBI) && in fixupCalleeSaveRestoreStackOffset()
2244 AArch64InstrInfo::isSEHInstruction(*Pop)) in emitEpilogue()
3727 const AArch64InstrInfo *TII = in emitUnrolled()
3774 const AArch64InstrInfo *TII = in emitLoop()
4301 const AArch64InstrInfo *TII = in inlineStackProbeLoopExactMultiple()
4355 const AArch64InstrInfo *TII = in inlineStackProbeFixed()
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H A DAArch64MIPeepholeOpt.cpp85 const AArch64InstrInfo *TII;
677 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64FalkorHWPFFix.cpp203 const AArch64InstrInfo *TII;
821 TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
H A DAArch64SIMDInstrOpt.cpp702 const AArch64InstrInfo *AAII = in runOnMachineFunction()
703 static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
H A DAArch64.td745 include "AArch64InstrInfo.td"
751 def AArch64InstrInfo : InstrInfo;
1768 let InstructionSet = AArch64InstrInfo;
H A DAArch64ExpandPseudoInsts.cpp51 const AArch64InstrInfo *TII;
1701 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
H A DAArch64InstrInfo.td1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
H A DAArch64ISelLowering.cpp2746 const AArch64InstrInfo &TII = in EmitDynamicProbedAlloc()
/freebsd-14.2/lib/clang/libllvm/
H A DMakefile1256 SRCS_MIN+= Target/AArch64/AArch64InstrInfo.cpp
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp512 const AArch64InstrInfo &TII;