1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 MLX5_EVENT_TYPE_CODING_GENERAL_OBJ_EVENT = 0x27, 67 }; 68 69 enum { 70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 75 }; 76 77 enum { 78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 79 }; 80 81 enum { 82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 84 }; 85 86 enum { 87 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 88 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 89 MLX5_CMD_OP_INIT_HCA = 0x102, 90 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 91 MLX5_CMD_OP_ENABLE_HCA = 0x104, 92 MLX5_CMD_OP_DISABLE_HCA = 0x105, 93 MLX5_CMD_OP_QUERY_PAGES = 0x107, 94 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 95 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 96 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 97 MLX5_CMD_OP_SET_ISSI = 0x10b, 98 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 99 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 100 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_CREATE_EQ = 0x301, 107 MLX5_CMD_OP_DESTROY_EQ = 0x302, 108 MLX5_CMD_OP_QUERY_EQ = 0x303, 109 MLX5_CMD_OP_GEN_EQE = 0x304, 110 MLX5_CMD_OP_CREATE_CQ = 0x400, 111 MLX5_CMD_OP_DESTROY_CQ = 0x401, 112 MLX5_CMD_OP_QUERY_CQ = 0x402, 113 MLX5_CMD_OP_MODIFY_CQ = 0x403, 114 MLX5_CMD_OP_CREATE_QP = 0x500, 115 MLX5_CMD_OP_DESTROY_QP = 0x501, 116 MLX5_CMD_OP_RST2INIT_QP = 0x502, 117 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 118 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 119 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 120 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 121 MLX5_CMD_OP_2ERR_QP = 0x507, 122 MLX5_CMD_OP_2RST_QP = 0x50a, 123 MLX5_CMD_OP_QUERY_QP = 0x50b, 124 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 125 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 126 MLX5_CMD_OP_CREATE_PSV = 0x600, 127 MLX5_CMD_OP_DESTROY_PSV = 0x601, 128 MLX5_CMD_OP_CREATE_SRQ = 0x700, 129 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 130 MLX5_CMD_OP_QUERY_SRQ = 0x702, 131 MLX5_CMD_OP_ARM_RQ = 0x703, 132 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 133 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 134 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 135 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 136 MLX5_CMD_OP_CREATE_DCT = 0x710, 137 MLX5_CMD_OP_DESTROY_DCT = 0x711, 138 MLX5_CMD_OP_DRAIN_DCT = 0x712, 139 MLX5_CMD_OP_QUERY_DCT = 0x713, 140 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 141 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 142 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 143 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 144 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 145 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 146 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 147 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 148 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 149 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 150 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 151 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 152 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 154 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 155 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 156 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 157 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 158 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 159 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 160 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 161 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 162 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 163 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 164 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 165 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 166 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 167 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 168 MLX5_CMD_OP_ALLOC_PD = 0x800, 169 MLX5_CMD_OP_DEALLOC_PD = 0x801, 170 MLX5_CMD_OP_ALLOC_UAR = 0x802, 171 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 172 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 173 MLX5_CMD_OP_ACCESS_REG = 0x805, 174 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 175 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 176 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 177 MLX5_CMD_OP_MAD_IFC = 0x50d, 178 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 179 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 180 MLX5_CMD_OP_NOP = 0x80d, 181 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 182 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 183 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 184 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 185 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 186 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 190 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 191 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 192 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 193 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 194 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 195 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 196 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 197 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 198 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 199 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 200 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 201 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 202 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 203 MLX5_CMD_OP_CREATE_LAG = 0x840, 204 MLX5_CMD_OP_MODIFY_LAG = 0x841, 205 MLX5_CMD_OP_QUERY_LAG = 0x842, 206 MLX5_CMD_OP_DESTROY_LAG = 0x843, 207 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 208 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 209 MLX5_CMD_OP_CREATE_TIR = 0x900, 210 MLX5_CMD_OP_MODIFY_TIR = 0x901, 211 MLX5_CMD_OP_DESTROY_TIR = 0x902, 212 MLX5_CMD_OP_QUERY_TIR = 0x903, 213 MLX5_CMD_OP_CREATE_SQ = 0x904, 214 MLX5_CMD_OP_MODIFY_SQ = 0x905, 215 MLX5_CMD_OP_DESTROY_SQ = 0x906, 216 MLX5_CMD_OP_QUERY_SQ = 0x907, 217 MLX5_CMD_OP_CREATE_RQ = 0x908, 218 MLX5_CMD_OP_MODIFY_RQ = 0x909, 219 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 220 MLX5_CMD_OP_QUERY_RQ = 0x90b, 221 MLX5_CMD_OP_CREATE_RMP = 0x90c, 222 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 223 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 224 MLX5_CMD_OP_QUERY_RMP = 0x90f, 225 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 226 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 227 MLX5_CMD_OP_CREATE_TIS = 0x912, 228 MLX5_CMD_OP_MODIFY_TIS = 0x913, 229 MLX5_CMD_OP_DESTROY_TIS = 0x914, 230 MLX5_CMD_OP_QUERY_TIS = 0x915, 231 MLX5_CMD_OP_CREATE_RQT = 0x916, 232 MLX5_CMD_OP_MODIFY_RQT = 0x917, 233 MLX5_CMD_OP_DESTROY_RQT = 0x918, 234 MLX5_CMD_OP_QUERY_RQT = 0x919, 235 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 236 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 237 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 238 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 239 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 240 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 241 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 242 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 243 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 244 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 245 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 246 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 247 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 248 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 249 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 250 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 260 261 }; 262 263 enum { 264 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 269 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 270 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 271 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 272 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 273 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 274 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 275 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 276 }; 277 278 enum { 279 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 280 }; 281 282 enum { 283 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 284 }; 285 286 enum { 287 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 288 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 289 }; 290 291 enum { 292 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1, 293 }; 294 295 struct mlx5_ifc_flow_table_fields_supported_bits { 296 u8 outer_dmac[0x1]; 297 u8 outer_smac[0x1]; 298 u8 outer_ether_type[0x1]; 299 u8 outer_ip_version[0x1]; 300 u8 outer_first_prio[0x1]; 301 u8 outer_first_cfi[0x1]; 302 u8 outer_first_vid[0x1]; 303 u8 reserved_1[0x1]; 304 u8 outer_second_prio[0x1]; 305 u8 outer_second_cfi[0x1]; 306 u8 outer_second_vid[0x1]; 307 u8 outer_ipv6_flow_label[0x1]; 308 u8 outer_sip[0x1]; 309 u8 outer_dip[0x1]; 310 u8 outer_frag[0x1]; 311 u8 outer_ip_protocol[0x1]; 312 u8 outer_ip_ecn[0x1]; 313 u8 outer_ip_dscp[0x1]; 314 u8 outer_udp_sport[0x1]; 315 u8 outer_udp_dport[0x1]; 316 u8 outer_tcp_sport[0x1]; 317 u8 outer_tcp_dport[0x1]; 318 u8 outer_tcp_flags[0x1]; 319 u8 outer_gre_protocol[0x1]; 320 u8 outer_gre_key[0x1]; 321 u8 outer_vxlan_vni[0x1]; 322 u8 outer_geneve_vni[0x1]; 323 u8 outer_geneve_oam[0x1]; 324 u8 outer_geneve_protocol_type[0x1]; 325 u8 outer_geneve_opt_len[0x1]; 326 u8 reserved_2[0x1]; 327 u8 source_eswitch_port[0x1]; 328 329 u8 inner_dmac[0x1]; 330 u8 inner_smac[0x1]; 331 u8 inner_ether_type[0x1]; 332 u8 inner_ip_version[0x1]; 333 u8 inner_first_prio[0x1]; 334 u8 inner_first_cfi[0x1]; 335 u8 inner_first_vid[0x1]; 336 u8 reserved_4[0x1]; 337 u8 inner_second_prio[0x1]; 338 u8 inner_second_cfi[0x1]; 339 u8 inner_second_vid[0x1]; 340 u8 inner_ipv6_flow_label[0x1]; 341 u8 inner_sip[0x1]; 342 u8 inner_dip[0x1]; 343 u8 inner_frag[0x1]; 344 u8 inner_ip_protocol[0x1]; 345 u8 inner_ip_ecn[0x1]; 346 u8 inner_ip_dscp[0x1]; 347 u8 inner_udp_sport[0x1]; 348 u8 inner_udp_dport[0x1]; 349 u8 inner_tcp_sport[0x1]; 350 u8 inner_tcp_dport[0x1]; 351 u8 inner_tcp_flags[0x1]; 352 u8 reserved_5[0x9]; 353 354 u8 reserved_6[0x1a]; 355 u8 bth_dst_qp[0x1]; 356 u8 reserved_7[0x4]; 357 u8 source_sqn[0x1]; 358 359 u8 reserved_8[0x20]; 360 }; 361 362 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 363 u8 ingress_general_high[0x20]; 364 365 u8 ingress_general_low[0x20]; 366 367 u8 ingress_policy_engine_high[0x20]; 368 369 u8 ingress_policy_engine_low[0x20]; 370 371 u8 ingress_vlan_membership_high[0x20]; 372 373 u8 ingress_vlan_membership_low[0x20]; 374 375 u8 ingress_tag_frame_type_high[0x20]; 376 377 u8 ingress_tag_frame_type_low[0x20]; 378 379 u8 egress_vlan_membership_high[0x20]; 380 381 u8 egress_vlan_membership_low[0x20]; 382 383 u8 loopback_filter_high[0x20]; 384 385 u8 loopback_filter_low[0x20]; 386 387 u8 egress_general_high[0x20]; 388 389 u8 egress_general_low[0x20]; 390 391 u8 reserved_at_1c0[0x40]; 392 393 u8 egress_hoq_high[0x20]; 394 395 u8 egress_hoq_low[0x20]; 396 397 u8 port_isolation_high[0x20]; 398 399 u8 port_isolation_low[0x20]; 400 401 u8 egress_policy_engine_high[0x20]; 402 403 u8 egress_policy_engine_low[0x20]; 404 405 u8 ingress_tx_link_down_high[0x20]; 406 407 u8 ingress_tx_link_down_low[0x20]; 408 409 u8 egress_stp_filter_high[0x20]; 410 411 u8 egress_stp_filter_low[0x20]; 412 413 u8 egress_hoq_stall_high[0x20]; 414 415 u8 egress_hoq_stall_low[0x20]; 416 417 u8 reserved_at_340[0x440]; 418 }; 419 struct mlx5_ifc_flow_table_prop_layout_bits { 420 u8 ft_support[0x1]; 421 u8 flow_tag[0x1]; 422 u8 flow_counter[0x1]; 423 u8 flow_modify_en[0x1]; 424 u8 modify_root[0x1]; 425 u8 identified_miss_table[0x1]; 426 u8 flow_table_modify[0x1]; 427 u8 encap[0x1]; 428 u8 decap[0x1]; 429 u8 reset_root_to_default[0x1]; 430 u8 reserved_at_a[0x16]; 431 432 u8 reserved_at_20[0x2]; 433 u8 log_max_ft_size[0x6]; 434 u8 reserved_at_28[0x10]; 435 u8 max_ft_level[0x8]; 436 437 u8 reserved_at_40[0x20]; 438 439 u8 reserved_at_60[0x18]; 440 u8 log_max_ft_num[0x8]; 441 442 u8 reserved_at_80[0x10]; 443 u8 log_max_flow_counter[0x8]; 444 u8 log_max_destination[0x8]; 445 446 u8 reserved_at_a0[0x18]; 447 u8 log_max_flow[0x8]; 448 449 u8 reserved_at_c0[0x40]; 450 451 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 452 453 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 454 }; 455 456 struct mlx5_ifc_odp_per_transport_service_cap_bits { 457 u8 send[0x1]; 458 u8 receive[0x1]; 459 u8 write[0x1]; 460 u8 read[0x1]; 461 u8 atomic[0x1]; 462 u8 srq_receive[0x1]; 463 u8 reserved_0[0x1a]; 464 }; 465 466 struct mlx5_ifc_flow_counter_list_bits { 467 u8 reserved_0[0x10]; 468 u8 flow_counter_id[0x10]; 469 470 u8 reserved_1[0x20]; 471 }; 472 473 enum { 474 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 475 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 476 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 477 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 478 }; 479 480 struct mlx5_ifc_dest_format_struct_bits { 481 u8 destination_type[0x8]; 482 u8 destination_id[0x18]; 483 484 u8 reserved_0[0x20]; 485 }; 486 487 struct mlx5_ifc_ipv4_layout_bits { 488 u8 reserved_at_0[0x60]; 489 490 u8 ipv4[0x20]; 491 }; 492 493 struct mlx5_ifc_ipv6_layout_bits { 494 u8 ipv6[16][0x8]; 495 }; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 500 u8 reserved_at_0[0x80]; 501 }; 502 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 504 u8 smac_47_16[0x20]; 505 506 u8 smac_15_0[0x10]; 507 u8 ethertype[0x10]; 508 509 u8 dmac_47_16[0x20]; 510 511 u8 dmac_15_0[0x10]; 512 u8 first_prio[0x3]; 513 u8 first_cfi[0x1]; 514 u8 first_vid[0xc]; 515 516 u8 ip_protocol[0x8]; 517 u8 ip_dscp[0x6]; 518 u8 ip_ecn[0x2]; 519 u8 cvlan_tag[0x1]; 520 u8 svlan_tag[0x1]; 521 u8 frag[0x1]; 522 u8 ip_version[0x4]; 523 u8 tcp_flags[0x9]; 524 525 u8 tcp_sport[0x10]; 526 u8 tcp_dport[0x10]; 527 528 u8 reserved_2[0x20]; 529 530 u8 udp_sport[0x10]; 531 u8 udp_dport[0x10]; 532 533 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 534 535 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 536 }; 537 538 struct mlx5_ifc_fte_match_set_misc_bits { 539 u8 reserved_0[0x8]; 540 u8 source_sqn[0x18]; 541 542 u8 reserved_1[0x10]; 543 u8 source_port[0x10]; 544 545 u8 outer_second_prio[0x3]; 546 u8 outer_second_cfi[0x1]; 547 u8 outer_second_vid[0xc]; 548 u8 inner_second_prio[0x3]; 549 u8 inner_second_cfi[0x1]; 550 u8 inner_second_vid[0xc]; 551 552 u8 outer_second_vlan_tag[0x1]; 553 u8 inner_second_vlan_tag[0x1]; 554 u8 reserved_2[0xe]; 555 u8 gre_protocol[0x10]; 556 557 u8 gre_key_h[0x18]; 558 u8 gre_key_l[0x8]; 559 560 u8 vxlan_vni[0x18]; 561 u8 reserved_3[0x8]; 562 563 u8 geneve_vni[0x18]; 564 u8 reserved4[0x7]; 565 u8 geneve_oam[0x1]; 566 567 u8 reserved_5[0xc]; 568 u8 outer_ipv6_flow_label[0x14]; 569 570 u8 reserved_6[0xc]; 571 u8 inner_ipv6_flow_label[0x14]; 572 573 u8 reserved_7[0xa]; 574 u8 geneve_opt_len[0x6]; 575 u8 geneve_protocol_type[0x10]; 576 577 u8 reserved_8[0x8]; 578 u8 bth_dst_qp[0x18]; 579 580 u8 reserved_9[0xa0]; 581 }; 582 583 struct mlx5_ifc_cmd_pas_bits { 584 u8 pa_h[0x20]; 585 586 u8 pa_l[0x14]; 587 u8 reserved_0[0xc]; 588 }; 589 590 struct mlx5_ifc_uint64_bits { 591 u8 hi[0x20]; 592 593 u8 lo[0x20]; 594 }; 595 596 struct mlx5_ifc_application_prio_entry_bits { 597 u8 reserved_0[0x8]; 598 u8 priority[0x3]; 599 u8 reserved_1[0x2]; 600 u8 sel[0x3]; 601 u8 protocol_id[0x10]; 602 }; 603 604 struct mlx5_ifc_nodnic_ring_doorbell_bits { 605 u8 reserved_0[0x8]; 606 u8 ring_pi[0x10]; 607 u8 reserved_1[0x8]; 608 }; 609 610 enum { 611 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 612 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 613 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 614 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 615 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 616 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 617 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 618 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 619 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 620 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 621 }; 622 623 struct mlx5_ifc_ads_bits { 624 u8 fl[0x1]; 625 u8 free_ar[0x1]; 626 u8 reserved_0[0xe]; 627 u8 pkey_index[0x10]; 628 629 u8 reserved_1[0x8]; 630 u8 grh[0x1]; 631 u8 mlid[0x7]; 632 u8 rlid[0x10]; 633 634 u8 ack_timeout[0x5]; 635 u8 reserved_2[0x3]; 636 u8 src_addr_index[0x8]; 637 u8 log_rtm[0x4]; 638 u8 stat_rate[0x4]; 639 u8 hop_limit[0x8]; 640 641 u8 reserved_3[0x4]; 642 u8 tclass[0x8]; 643 u8 flow_label[0x14]; 644 645 u8 rgid_rip[16][0x8]; 646 647 u8 reserved_4[0x4]; 648 u8 f_dscp[0x1]; 649 u8 f_ecn[0x1]; 650 u8 reserved_5[0x1]; 651 u8 f_eth_prio[0x1]; 652 u8 ecn[0x2]; 653 u8 dscp[0x6]; 654 u8 udp_sport[0x10]; 655 656 u8 dei_cfi[0x1]; 657 u8 eth_prio[0x3]; 658 u8 sl[0x4]; 659 u8 port[0x8]; 660 u8 rmac_47_32[0x10]; 661 662 u8 rmac_31_0[0x20]; 663 }; 664 665 struct mlx5_ifc_diagnostic_counter_cap_bits { 666 u8 sync[0x1]; 667 u8 reserved_0[0xf]; 668 u8 counter_id[0x10]; 669 }; 670 671 struct mlx5_ifc_debug_cap_bits { 672 u8 reserved_0[0x18]; 673 u8 log_max_samples[0x8]; 674 675 u8 single[0x1]; 676 u8 repetitive[0x1]; 677 u8 health_mon_rx_activity[0x1]; 678 u8 reserved_1[0x15]; 679 u8 log_min_sample_period[0x8]; 680 681 u8 reserved_2[0x1c0]; 682 683 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 684 }; 685 686 struct mlx5_ifc_qos_cap_bits { 687 u8 packet_pacing[0x1]; 688 u8 esw_scheduling[0x1]; 689 u8 esw_bw_share[0x1]; 690 u8 esw_rate_limit[0x1]; 691 u8 hll[0x1]; 692 u8 packet_pacing_burst_bound[0x1]; 693 u8 packet_pacing_typical_size[0x1]; 694 u8 reserved_at_7[0x19]; 695 696 u8 reserved_at_20[0xA]; 697 u8 qos_remap_pp[0x1]; 698 u8 reserved_at_2b[0x15]; 699 700 u8 packet_pacing_max_rate[0x20]; 701 702 u8 packet_pacing_min_rate[0x20]; 703 704 u8 reserved_at_80[0x10]; 705 u8 packet_pacing_rate_table_size[0x10]; 706 707 u8 esw_element_type[0x10]; 708 u8 esw_tsar_type[0x10]; 709 710 u8 reserved_at_c0[0x10]; 711 u8 max_qos_para_vport[0x10]; 712 713 u8 max_tsar_bw_share[0x20]; 714 715 u8 reserved_at_100[0x700]; 716 }; 717 718 struct mlx5_ifc_snapshot_cap_bits { 719 u8 reserved_0[0x1d]; 720 u8 suspend_qp_uc[0x1]; 721 u8 suspend_qp_ud[0x1]; 722 u8 suspend_qp_rc[0x1]; 723 724 u8 reserved_1[0x1c]; 725 u8 restore_pd[0x1]; 726 u8 restore_uar[0x1]; 727 u8 restore_mkey[0x1]; 728 u8 restore_qp[0x1]; 729 730 u8 reserved_2[0x1e]; 731 u8 named_mkey[0x1]; 732 u8 named_qp[0x1]; 733 734 u8 reserved_3[0x7a0]; 735 }; 736 737 struct mlx5_ifc_e_switch_cap_bits { 738 u8 vport_svlan_strip[0x1]; 739 u8 vport_cvlan_strip[0x1]; 740 u8 vport_svlan_insert[0x1]; 741 u8 vport_cvlan_insert_if_not_exist[0x1]; 742 u8 vport_cvlan_insert_overwrite[0x1]; 743 744 u8 reserved_0[0x19]; 745 746 u8 nic_vport_node_guid_modify[0x1]; 747 u8 nic_vport_port_guid_modify[0x1]; 748 749 u8 reserved_1[0x7e0]; 750 }; 751 752 struct mlx5_ifc_flow_table_eswitch_cap_bits { 753 u8 reserved_0[0x200]; 754 755 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 756 757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 758 759 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 760 761 u8 reserved_1[0x7800]; 762 }; 763 764 struct mlx5_ifc_flow_table_nic_cap_bits { 765 u8 nic_rx_multi_path_tirs[0x1]; 766 u8 nic_rx_multi_path_tirs_fts[0x1]; 767 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 768 u8 reserved_at_3[0x1fd]; 769 770 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 771 772 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 773 774 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 775 776 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 777 778 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 779 780 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 781 782 u8 reserved_1[0x7200]; 783 }; 784 785 struct mlx5_ifc_pddr_module_info_bits { 786 u8 cable_technology[0x8]; 787 u8 cable_breakout[0x8]; 788 u8 ext_ethernet_compliance_code[0x8]; 789 u8 ethernet_compliance_code[0x8]; 790 791 u8 cable_type[0x4]; 792 u8 cable_vendor[0x4]; 793 u8 cable_length[0x8]; 794 u8 cable_identifier[0x8]; 795 u8 cable_power_class[0x8]; 796 797 u8 reserved_at_40[0x8]; 798 u8 cable_rx_amp[0x8]; 799 u8 cable_rx_emphasis[0x8]; 800 u8 cable_tx_equalization[0x8]; 801 802 u8 reserved_at_60[0x8]; 803 u8 cable_attenuation_12g[0x8]; 804 u8 cable_attenuation_7g[0x8]; 805 u8 cable_attenuation_5g[0x8]; 806 807 u8 reserved_at_80[0x8]; 808 u8 rx_cdr_cap[0x4]; 809 u8 tx_cdr_cap[0x4]; 810 u8 reserved_at_90[0x4]; 811 u8 rx_cdr_state[0x4]; 812 u8 reserved_at_98[0x4]; 813 u8 tx_cdr_state[0x4]; 814 815 u8 vendor_name[16][0x8]; 816 817 u8 vendor_pn[16][0x8]; 818 819 u8 vendor_rev[0x20]; 820 821 u8 fw_version[0x20]; 822 823 u8 vendor_sn[16][0x8]; 824 825 u8 temperature[0x10]; 826 u8 voltage[0x10]; 827 828 u8 rx_power_lane0[0x10]; 829 u8 rx_power_lane1[0x10]; 830 831 u8 rx_power_lane2[0x10]; 832 u8 rx_power_lane3[0x10]; 833 834 u8 reserved_at_2c0[0x40]; 835 836 u8 tx_power_lane0[0x10]; 837 u8 tx_power_lane1[0x10]; 838 839 u8 tx_power_lane2[0x10]; 840 u8 tx_power_lane3[0x10]; 841 842 u8 reserved_at_340[0x40]; 843 844 u8 tx_bias_lane0[0x10]; 845 u8 tx_bias_lane1[0x10]; 846 847 u8 tx_bias_lane2[0x10]; 848 u8 tx_bias_lane3[0x10]; 849 850 u8 reserved_at_3c0[0x40]; 851 852 u8 temperature_high_th[0x10]; 853 u8 temperature_low_th[0x10]; 854 855 u8 voltage_high_th[0x10]; 856 u8 voltage_low_th[0x10]; 857 858 u8 rx_power_high_th[0x10]; 859 u8 rx_power_low_th[0x10]; 860 861 u8 tx_power_high_th[0x10]; 862 u8 tx_power_low_th[0x10]; 863 864 u8 tx_bias_high_th[0x10]; 865 u8 tx_bias_low_th[0x10]; 866 867 u8 reserved_at_4a0[0x10]; 868 u8 wavelength[0x10]; 869 870 u8 reserved_at_4c0[0x300]; 871 }; 872 873 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 874 u8 csum_cap[0x1]; 875 u8 vlan_cap[0x1]; 876 u8 lro_cap[0x1]; 877 u8 lro_psh_flag[0x1]; 878 u8 lro_time_stamp[0x1]; 879 u8 lro_max_msg_sz_mode[0x2]; 880 u8 wqe_vlan_insert[0x1]; 881 u8 self_lb_en_modifiable[0x1]; 882 u8 self_lb_mc[0x1]; 883 u8 self_lb_uc[0x1]; 884 u8 max_lso_cap[0x5]; 885 u8 multi_pkt_send_wqe[0x2]; 886 u8 wqe_inline_mode[0x2]; 887 u8 rss_ind_tbl_cap[0x4]; 888 u8 reg_umr_sq[0x1]; 889 u8 scatter_fcs[0x1]; 890 u8 enhanced_multi_pkt_send_wqe[0x1]; 891 u8 tunnel_lso_const_out_ip_id[0x1]; 892 u8 tunnel_lro_gre[0x1]; 893 u8 tunnel_lro_vxlan[0x1]; 894 u8 tunnel_statless_gre[0x1]; 895 u8 tunnel_stateless_vxlan[0x1]; 896 897 u8 swp[0x1]; 898 u8 swp_csum[0x1]; 899 u8 swp_lso[0x1]; 900 u8 reserved_2[0x1b]; 901 u8 max_geneve_opt_len[0x1]; 902 u8 tunnel_stateless_geneve_rx[0x1]; 903 904 u8 reserved_3[0x10]; 905 u8 lro_min_mss_size[0x10]; 906 907 u8 reserved_4[0x120]; 908 909 u8 lro_timer_supported_periods[4][0x20]; 910 911 u8 reserved_5[0x600]; 912 }; 913 914 enum { 915 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 916 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 917 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 918 }; 919 920 enum { 921 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 922 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 923 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 924 }; 925 926 struct mlx5_ifc_roce_cap_bits { 927 u8 roce_apm[0x1]; 928 u8 rts2rts_primary_eth_prio[0x1]; 929 u8 roce_rx_allow_untagged[0x1]; 930 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 931 u8 reserved_at_4[0x1a]; 932 u8 qp_ts_format[0x2]; 933 934 u8 reserved_1[0x60]; 935 936 u8 reserved_2[0xc]; 937 u8 l3_type[0x4]; 938 u8 reserved_3[0x8]; 939 u8 roce_version[0x8]; 940 941 u8 reserved_4[0x10]; 942 u8 r_roce_dest_udp_port[0x10]; 943 944 u8 r_roce_max_src_udp_port[0x10]; 945 u8 r_roce_min_src_udp_port[0x10]; 946 947 u8 reserved_5[0x10]; 948 u8 roce_address_table_size[0x10]; 949 950 u8 reserved_6[0x700]; 951 }; 952 953 enum { 954 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 955 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 956 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 962 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 963 }; 964 965 enum { 966 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 967 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 968 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 969 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 970 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 972 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 973 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 974 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 975 }; 976 977 struct mlx5_ifc_atomic_caps_bits { 978 u8 reserved_0[0x40]; 979 980 u8 atomic_req_8B_endianess_mode[0x2]; 981 u8 reserved_1[0x4]; 982 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 983 984 u8 reserved_2[0x19]; 985 986 u8 reserved_3[0x20]; 987 988 u8 reserved_4[0x10]; 989 u8 atomic_operations[0x10]; 990 991 u8 reserved_5[0x10]; 992 u8 atomic_size_qp[0x10]; 993 994 u8 reserved_6[0x10]; 995 u8 atomic_size_dc[0x10]; 996 997 u8 reserved_7[0x720]; 998 }; 999 1000 struct mlx5_ifc_odp_cap_bits { 1001 u8 reserved_0[0x40]; 1002 1003 u8 sig[0x1]; 1004 u8 reserved_1[0x1f]; 1005 1006 u8 reserved_2[0x20]; 1007 1008 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1009 1010 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1011 1012 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1013 1014 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1015 1016 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1017 1018 u8 reserved_3[0x6e0]; 1019 }; 1020 1021 enum { 1022 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1023 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1024 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1025 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1026 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1027 }; 1028 1029 enum { 1030 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1031 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1032 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1033 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1034 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1035 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1036 }; 1037 1038 enum { 1039 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1040 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1041 }; 1042 1043 enum { 1044 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1045 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1046 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1047 }; 1048 1049 enum { 1050 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1051 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1052 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1053 }; 1054 1055 enum { 1056 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1057 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1058 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1059 }; 1060 1061 struct mlx5_ifc_cmd_hca_cap_bits { 1062 u8 reserved_0[0x80]; 1063 1064 u8 log_max_srq_sz[0x8]; 1065 u8 log_max_qp_sz[0x8]; 1066 u8 reserved_1[0xb]; 1067 u8 log_max_qp[0x5]; 1068 1069 u8 reserved_2[0xb]; 1070 u8 log_max_srq[0x5]; 1071 u8 reserved_3[0x10]; 1072 1073 u8 reserved_4[0x8]; 1074 u8 log_max_cq_sz[0x8]; 1075 u8 relaxed_ordering_write_umr[0x1]; 1076 u8 relaxed_ordering_read_umr[0x1]; 1077 u8 reserved_5[0x9]; 1078 u8 log_max_cq[0x5]; 1079 1080 u8 log_max_eq_sz[0x8]; 1081 u8 relaxed_ordering_write[0x1]; 1082 u8 relaxed_ordering_read[0x1]; 1083 u8 log_max_mkey[0x6]; 1084 u8 reserved_7[0xb]; 1085 u8 fast_teardown[0x1]; 1086 u8 log_max_eq[0x4]; 1087 1088 u8 max_indirection[0x8]; 1089 u8 reserved_8[0x1]; 1090 u8 log_max_mrw_sz[0x7]; 1091 u8 force_teardown[0x1]; 1092 u8 reserved_9[0x1]; 1093 u8 log_max_bsf_list_size[0x6]; 1094 u8 reserved_10[0x2]; 1095 u8 log_max_klm_list_size[0x6]; 1096 1097 u8 reserved_11[0xa]; 1098 u8 log_max_ra_req_dc[0x6]; 1099 u8 reserved_12[0xa]; 1100 u8 log_max_ra_res_dc[0x6]; 1101 1102 u8 reserved_13[0xa]; 1103 u8 log_max_ra_req_qp[0x6]; 1104 u8 reserved_14[0xa]; 1105 u8 log_max_ra_res_qp[0x6]; 1106 1107 u8 pad_cap[0x1]; 1108 u8 cc_query_allowed[0x1]; 1109 u8 cc_modify_allowed[0x1]; 1110 u8 start_pad[0x1]; 1111 u8 cache_line_128byte[0x1]; 1112 u8 reserved_at_165[0xa]; 1113 u8 qcam_reg[0x1]; 1114 u8 gid_table_size[0x10]; 1115 1116 u8 out_of_seq_cnt[0x1]; 1117 u8 vport_counters[0x1]; 1118 u8 retransmission_q_counters[0x1]; 1119 u8 debug[0x1]; 1120 u8 modify_rq_counters_set_id[0x1]; 1121 u8 rq_delay_drop[0x1]; 1122 u8 max_qp_cnt[0xa]; 1123 u8 pkey_table_size[0x10]; 1124 1125 u8 vport_group_manager[0x1]; 1126 u8 vhca_group_manager[0x1]; 1127 u8 ib_virt[0x1]; 1128 u8 eth_virt[0x1]; 1129 u8 reserved_17[0x1]; 1130 u8 ets[0x1]; 1131 u8 nic_flow_table[0x1]; 1132 u8 eswitch_flow_table[0x1]; 1133 u8 reserved_18[0x1]; 1134 u8 mcam_reg[0x1]; 1135 u8 pcam_reg[0x1]; 1136 u8 local_ca_ack_delay[0x5]; 1137 u8 port_module_event[0x1]; 1138 u8 reserved_19[0x5]; 1139 u8 port_type[0x2]; 1140 u8 num_ports[0x8]; 1141 1142 u8 snapshot[0x1]; 1143 u8 reserved_20[0x2]; 1144 u8 log_max_msg[0x5]; 1145 u8 reserved_21[0x4]; 1146 u8 max_tc[0x4]; 1147 u8 temp_warn_event[0x1]; 1148 u8 dcbx[0x1]; 1149 u8 general_notification_event[0x1]; 1150 u8 reserved_at_1d3[0x2]; 1151 u8 fpga[0x1]; 1152 u8 rol_s[0x1]; 1153 u8 rol_g[0x1]; 1154 u8 reserved_23[0x1]; 1155 u8 wol_s[0x1]; 1156 u8 wol_g[0x1]; 1157 u8 wol_a[0x1]; 1158 u8 wol_b[0x1]; 1159 u8 wol_m[0x1]; 1160 u8 wol_u[0x1]; 1161 u8 wol_p[0x1]; 1162 1163 u8 stat_rate_support[0x10]; 1164 u8 reserved_24[0xc]; 1165 u8 cqe_version[0x4]; 1166 1167 u8 compact_address_vector[0x1]; 1168 u8 striding_rq[0x1]; 1169 u8 reserved_25[0x1]; 1170 u8 ipoib_enhanced_offloads[0x1]; 1171 u8 ipoib_ipoib_offloads[0x1]; 1172 u8 reserved_26[0x8]; 1173 u8 dc_connect_qp[0x1]; 1174 u8 dc_cnak_trace[0x1]; 1175 u8 drain_sigerr[0x1]; 1176 u8 cmdif_checksum[0x2]; 1177 u8 sigerr_cqe[0x1]; 1178 u8 reserved_27[0x1]; 1179 u8 wq_signature[0x1]; 1180 u8 sctr_data_cqe[0x1]; 1181 u8 reserved_28[0x1]; 1182 u8 sho[0x1]; 1183 u8 tph[0x1]; 1184 u8 rf[0x1]; 1185 u8 dct[0x1]; 1186 u8 qos[0x1]; 1187 u8 eth_net_offloads[0x1]; 1188 u8 roce[0x1]; 1189 u8 atomic[0x1]; 1190 u8 reserved_30[0x1]; 1191 1192 u8 cq_oi[0x1]; 1193 u8 cq_resize[0x1]; 1194 u8 cq_moderation[0x1]; 1195 u8 cq_period_mode_modify[0x1]; 1196 u8 cq_invalidate[0x1]; 1197 u8 reserved_at_225[0x1]; 1198 u8 cq_eq_remap[0x1]; 1199 u8 pg[0x1]; 1200 u8 block_lb_mc[0x1]; 1201 u8 exponential_backoff[0x1]; 1202 u8 scqe_break_moderation[0x1]; 1203 u8 cq_period_start_from_cqe[0x1]; 1204 u8 cd[0x1]; 1205 u8 atm[0x1]; 1206 u8 apm[0x1]; 1207 u8 imaicl[0x1]; 1208 u8 reserved_32[0x6]; 1209 u8 qkv[0x1]; 1210 u8 pkv[0x1]; 1211 u8 set_deth_sqpn[0x1]; 1212 u8 reserved_33[0x3]; 1213 u8 xrc[0x1]; 1214 u8 ud[0x1]; 1215 u8 uc[0x1]; 1216 u8 rc[0x1]; 1217 1218 u8 uar_4k[0x1]; 1219 u8 reserved_at_241[0x9]; 1220 u8 uar_sz[0x6]; 1221 u8 reserved_35[0x8]; 1222 u8 log_pg_sz[0x8]; 1223 1224 u8 bf[0x1]; 1225 u8 driver_version[0x1]; 1226 u8 pad_tx_eth_packet[0x1]; 1227 u8 reserved_36[0x8]; 1228 u8 log_bf_reg_size[0x5]; 1229 u8 reserved_37[0x10]; 1230 1231 u8 num_of_diagnostic_counters[0x10]; 1232 u8 max_wqe_sz_sq[0x10]; 1233 1234 u8 reserved_38[0x10]; 1235 u8 max_wqe_sz_rq[0x10]; 1236 1237 u8 reserved_39[0x10]; 1238 u8 max_wqe_sz_sq_dc[0x10]; 1239 1240 u8 reserved_40[0x7]; 1241 u8 max_qp_mcg[0x19]; 1242 1243 u8 reserved_41[0x18]; 1244 u8 log_max_mcg[0x8]; 1245 1246 u8 reserved_42[0x3]; 1247 u8 log_max_transport_domain[0x5]; 1248 u8 reserved_43[0x3]; 1249 u8 log_max_pd[0x5]; 1250 u8 reserved_44[0xb]; 1251 u8 log_max_xrcd[0x5]; 1252 1253 u8 nic_receive_steering_discard[0x1]; 1254 u8 reserved_45[0x7]; 1255 u8 log_max_flow_counter_bulk[0x8]; 1256 u8 max_flow_counter[0x10]; 1257 1258 u8 reserved_46[0x3]; 1259 u8 log_max_rq[0x5]; 1260 u8 reserved_47[0x3]; 1261 u8 log_max_sq[0x5]; 1262 u8 reserved_48[0x3]; 1263 u8 log_max_tir[0x5]; 1264 u8 reserved_49[0x3]; 1265 u8 log_max_tis[0x5]; 1266 1267 u8 basic_cyclic_rcv_wqe[0x1]; 1268 u8 reserved_50[0x2]; 1269 u8 log_max_rmp[0x5]; 1270 u8 reserved_51[0x3]; 1271 u8 log_max_rqt[0x5]; 1272 u8 reserved_52[0x3]; 1273 u8 log_max_rqt_size[0x5]; 1274 u8 reserved_53[0x3]; 1275 u8 log_max_tis_per_sq[0x5]; 1276 1277 u8 reserved_54[0x3]; 1278 u8 log_max_stride_sz_rq[0x5]; 1279 u8 reserved_55[0x3]; 1280 u8 log_min_stride_sz_rq[0x5]; 1281 u8 reserved_56[0x3]; 1282 u8 log_max_stride_sz_sq[0x5]; 1283 u8 reserved_57[0x3]; 1284 u8 log_min_stride_sz_sq[0x5]; 1285 1286 u8 reserved_58[0x1b]; 1287 u8 log_max_wq_sz[0x5]; 1288 1289 u8 nic_vport_change_event[0x1]; 1290 u8 disable_local_lb_uc[0x1]; 1291 u8 disable_local_lb_mc[0x1]; 1292 u8 reserved_59[0x8]; 1293 u8 log_max_vlan_list[0x5]; 1294 u8 reserved_60[0x3]; 1295 u8 log_max_current_mc_list[0x5]; 1296 u8 reserved_61[0x3]; 1297 u8 log_max_current_uc_list[0x5]; 1298 1299 u8 general_obj_types[0x40]; 1300 1301 u8 sq_ts_format[0x2]; 1302 u8 rq_ts_format[0x2]; 1303 u8 reserved_at_444[0x4]; 1304 u8 create_qp_start_hint[0x18]; 1305 1306 u8 reserved_at_460[0x3]; 1307 u8 log_max_uctx[0x5]; 1308 u8 reserved_at_468[0x3]; 1309 u8 log_max_umem[0x5]; 1310 u8 max_num_eqs[0x10]; 1311 1312 u8 reserved_at_480[0x1]; 1313 u8 tls_tx[0x1]; 1314 u8 reserved_at_482[0x1]; 1315 u8 log_max_l2_table[0x5]; 1316 u8 reserved_64[0x8]; 1317 u8 log_uar_page_sz[0x10]; 1318 1319 u8 reserved_65[0x20]; 1320 1321 u8 device_frequency_mhz[0x20]; 1322 1323 u8 device_frequency_khz[0x20]; 1324 1325 u8 reserved_at_500[0x20]; 1326 u8 num_of_uars_per_page[0x20]; 1327 u8 reserved_at_540[0x40]; 1328 1329 u8 log_max_atomic_size_qp[0x8]; 1330 u8 reserved_67[0x10]; 1331 u8 log_max_atomic_size_dc[0x8]; 1332 1333 u8 reserved_at_5a0[0x13]; 1334 u8 log_max_dek[0x5]; 1335 u8 reserved_at_5b8[0x4]; 1336 u8 mini_cqe_resp_stride_index[0x1]; 1337 u8 cqe_128_always[0x1]; 1338 u8 cqe_compression_128b[0x1]; 1339 1340 u8 cqe_compression[0x1]; 1341 1342 u8 cqe_compression_timeout[0x10]; 1343 u8 cqe_compression_max_num[0x10]; 1344 1345 u8 reserved_69[0x220]; 1346 }; 1347 1348 enum mlx5_flow_destination_type { 1349 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1350 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1351 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1352 }; 1353 1354 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1355 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1356 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1357 u8 reserved_0[0x40]; 1358 }; 1359 1360 struct mlx5_ifc_fte_match_param_bits { 1361 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1362 1363 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1364 1365 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1366 1367 u8 reserved_0[0xa00]; 1368 }; 1369 1370 enum { 1371 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1372 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1373 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1374 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1375 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1376 }; 1377 1378 struct mlx5_ifc_rx_hash_field_select_bits { 1379 u8 l3_prot_type[0x1]; 1380 u8 l4_prot_type[0x1]; 1381 u8 selected_fields[0x1e]; 1382 }; 1383 1384 struct mlx5_ifc_tls_capabilities_bits { 1385 u8 tls_1_2_aes_gcm_128[0x1]; 1386 u8 tls_1_3_aes_gcm_128[0x1]; 1387 u8 tls_1_2_aes_gcm_256[0x1]; 1388 u8 tls_1_3_aes_gcm_256[0x1]; 1389 u8 reserved_at_4[0x1c]; 1390 1391 u8 reserved_at_20[0x7e0]; 1392 }; 1393 1394 enum { 1395 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1396 MLX5_WQ_TYPE_CYCLIC = 0x1, 1397 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1398 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1399 }; 1400 1401 enum rq_type { 1402 RQ_TYPE_NONE, 1403 RQ_TYPE_STRIDE, 1404 }; 1405 1406 enum { 1407 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1408 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1409 }; 1410 1411 struct mlx5_ifc_wq_bits { 1412 u8 wq_type[0x4]; 1413 u8 wq_signature[0x1]; 1414 u8 end_padding_mode[0x2]; 1415 u8 cd_slave[0x1]; 1416 u8 reserved_0[0x18]; 1417 1418 u8 hds_skip_first_sge[0x1]; 1419 u8 log2_hds_buf_size[0x3]; 1420 u8 reserved_1[0x7]; 1421 u8 page_offset[0x5]; 1422 u8 lwm[0x10]; 1423 1424 u8 reserved_2[0x8]; 1425 u8 pd[0x18]; 1426 1427 u8 reserved_3[0x8]; 1428 u8 uar_page[0x18]; 1429 1430 u8 dbr_addr[0x40]; 1431 1432 u8 hw_counter[0x20]; 1433 1434 u8 sw_counter[0x20]; 1435 1436 u8 reserved_4[0xc]; 1437 u8 log_wq_stride[0x4]; 1438 u8 reserved_5[0x3]; 1439 u8 log_wq_pg_sz[0x5]; 1440 u8 reserved_6[0x3]; 1441 u8 log_wq_sz[0x5]; 1442 1443 u8 reserved_7[0x15]; 1444 u8 single_wqe_log_num_of_strides[0x3]; 1445 u8 two_byte_shift_en[0x1]; 1446 u8 reserved_8[0x4]; 1447 u8 single_stride_log_num_of_bytes[0x3]; 1448 1449 u8 reserved_9[0x4c0]; 1450 1451 struct mlx5_ifc_cmd_pas_bits pas[0]; 1452 }; 1453 1454 struct mlx5_ifc_rq_num_bits { 1455 u8 reserved_0[0x8]; 1456 u8 rq_num[0x18]; 1457 }; 1458 1459 struct mlx5_ifc_mac_address_layout_bits { 1460 u8 reserved_0[0x10]; 1461 u8 mac_addr_47_32[0x10]; 1462 1463 u8 mac_addr_31_0[0x20]; 1464 }; 1465 1466 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1467 u8 reserved_0[0xa0]; 1468 1469 u8 min_time_between_cnps[0x20]; 1470 1471 u8 reserved_1[0x12]; 1472 u8 cnp_dscp[0x6]; 1473 u8 reserved_2[0x4]; 1474 u8 cnp_prio_mode[0x1]; 1475 u8 cnp_802p_prio[0x3]; 1476 1477 u8 reserved_3[0x720]; 1478 }; 1479 1480 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1481 u8 reserved_0[0x60]; 1482 1483 u8 reserved_1[0x4]; 1484 u8 clamp_tgt_rate[0x1]; 1485 u8 reserved_2[0x3]; 1486 u8 clamp_tgt_rate_after_time_inc[0x1]; 1487 u8 reserved_3[0x17]; 1488 1489 u8 reserved_4[0x20]; 1490 1491 u8 rpg_time_reset[0x20]; 1492 1493 u8 rpg_byte_reset[0x20]; 1494 1495 u8 rpg_threshold[0x20]; 1496 1497 u8 rpg_max_rate[0x20]; 1498 1499 u8 rpg_ai_rate[0x20]; 1500 1501 u8 rpg_hai_rate[0x20]; 1502 1503 u8 rpg_gd[0x20]; 1504 1505 u8 rpg_min_dec_fac[0x20]; 1506 1507 u8 rpg_min_rate[0x20]; 1508 1509 u8 reserved_5[0xe0]; 1510 1511 u8 rate_to_set_on_first_cnp[0x20]; 1512 1513 u8 dce_tcp_g[0x20]; 1514 1515 u8 dce_tcp_rtt[0x20]; 1516 1517 u8 rate_reduce_monitor_period[0x20]; 1518 1519 u8 reserved_6[0x20]; 1520 1521 u8 initial_alpha_value[0x20]; 1522 1523 u8 reserved_7[0x4a0]; 1524 }; 1525 1526 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1527 u8 reserved_0[0x80]; 1528 1529 u8 rppp_max_rps[0x20]; 1530 1531 u8 rpg_time_reset[0x20]; 1532 1533 u8 rpg_byte_reset[0x20]; 1534 1535 u8 rpg_threshold[0x20]; 1536 1537 u8 rpg_max_rate[0x20]; 1538 1539 u8 rpg_ai_rate[0x20]; 1540 1541 u8 rpg_hai_rate[0x20]; 1542 1543 u8 rpg_gd[0x20]; 1544 1545 u8 rpg_min_dec_fac[0x20]; 1546 1547 u8 rpg_min_rate[0x20]; 1548 1549 u8 reserved_1[0x640]; 1550 }; 1551 1552 enum { 1553 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1554 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1555 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1556 }; 1557 1558 struct mlx5_ifc_resize_field_select_bits { 1559 u8 resize_field_select[0x20]; 1560 }; 1561 1562 enum { 1563 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1564 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1565 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1566 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1567 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1568 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1569 }; 1570 1571 struct mlx5_ifc_modify_field_select_bits { 1572 u8 modify_field_select[0x20]; 1573 }; 1574 1575 struct mlx5_ifc_field_select_r_roce_np_bits { 1576 u8 field_select_r_roce_np[0x20]; 1577 }; 1578 1579 enum { 1580 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1581 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1582 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1583 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1584 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1585 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1586 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1587 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1588 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1589 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1590 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1591 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1592 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1593 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1594 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1595 }; 1596 1597 struct mlx5_ifc_field_select_r_roce_rp_bits { 1598 u8 field_select_r_roce_rp[0x20]; 1599 }; 1600 1601 enum { 1602 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1603 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1604 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1605 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1606 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1607 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1608 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1609 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1610 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1611 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1612 }; 1613 1614 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1615 u8 field_select_8021qaurp[0x20]; 1616 }; 1617 1618 struct mlx5_ifc_pptb_reg_bits { 1619 u8 reserved_at_0[0x2]; 1620 u8 mm[0x2]; 1621 u8 reserved_at_4[0x4]; 1622 u8 local_port[0x8]; 1623 u8 reserved_at_10[0x6]; 1624 u8 cm[0x1]; 1625 u8 um[0x1]; 1626 u8 pm[0x8]; 1627 1628 u8 prio_x_buff[0x20]; 1629 1630 u8 pm_msb[0x8]; 1631 u8 reserved_at_48[0x10]; 1632 u8 ctrl_buff[0x4]; 1633 u8 untagged_buff[0x4]; 1634 }; 1635 1636 struct mlx5_ifc_dcbx_app_reg_bits { 1637 u8 reserved_0[0x8]; 1638 u8 port_number[0x8]; 1639 u8 reserved_1[0x10]; 1640 1641 u8 reserved_2[0x1a]; 1642 u8 num_app_prio[0x6]; 1643 1644 u8 reserved_3[0x40]; 1645 1646 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1647 }; 1648 1649 struct mlx5_ifc_dcbx_param_reg_bits { 1650 u8 dcbx_cee_cap[0x1]; 1651 u8 dcbx_ieee_cap[0x1]; 1652 u8 dcbx_standby_cap[0x1]; 1653 u8 reserved_0[0x5]; 1654 u8 port_number[0x8]; 1655 u8 reserved_1[0xa]; 1656 u8 max_application_table_size[0x6]; 1657 1658 u8 reserved_2[0x15]; 1659 u8 version_oper[0x3]; 1660 u8 reserved_3[0x5]; 1661 u8 version_admin[0x3]; 1662 1663 u8 willing_admin[0x1]; 1664 u8 reserved_4[0x3]; 1665 u8 pfc_cap_oper[0x4]; 1666 u8 reserved_5[0x4]; 1667 u8 pfc_cap_admin[0x4]; 1668 u8 reserved_6[0x4]; 1669 u8 num_of_tc_oper[0x4]; 1670 u8 reserved_7[0x4]; 1671 u8 num_of_tc_admin[0x4]; 1672 1673 u8 remote_willing[0x1]; 1674 u8 reserved_8[0x3]; 1675 u8 remote_pfc_cap[0x4]; 1676 u8 reserved_9[0x14]; 1677 u8 remote_num_of_tc[0x4]; 1678 1679 u8 reserved_10[0x18]; 1680 u8 error[0x8]; 1681 1682 u8 reserved_11[0x160]; 1683 }; 1684 1685 struct mlx5_ifc_qhll_bits { 1686 u8 reserved_at_0[0x8]; 1687 u8 local_port[0x8]; 1688 u8 reserved_at_10[0x10]; 1689 1690 u8 reserved_at_20[0x1b]; 1691 u8 hll_time[0x5]; 1692 1693 u8 stall_en[0x1]; 1694 u8 reserved_at_41[0x1c]; 1695 u8 stall_cnt[0x3]; 1696 }; 1697 1698 struct mlx5_ifc_qetcr_reg_bits { 1699 u8 operation_type[0x2]; 1700 u8 cap_local_admin[0x1]; 1701 u8 cap_remote_admin[0x1]; 1702 u8 reserved_0[0x4]; 1703 u8 port_number[0x8]; 1704 u8 reserved_1[0x10]; 1705 1706 u8 reserved_2[0x20]; 1707 1708 u8 tc[8][0x40]; 1709 1710 u8 global_configuration[0x40]; 1711 }; 1712 1713 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1714 u8 queue_address_63_32[0x20]; 1715 1716 u8 queue_address_31_12[0x14]; 1717 u8 reserved_0[0x6]; 1718 u8 log_size[0x6]; 1719 1720 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1721 1722 u8 reserved_1[0x8]; 1723 u8 queue_number[0x18]; 1724 1725 u8 q_key[0x20]; 1726 1727 u8 reserved_2[0x10]; 1728 u8 pkey_index[0x10]; 1729 1730 u8 reserved_3[0x40]; 1731 }; 1732 1733 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1734 u8 reserved_0[0x8]; 1735 u8 cq_ci[0x10]; 1736 u8 reserved_1[0x8]; 1737 }; 1738 1739 enum { 1740 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1741 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1742 }; 1743 1744 enum { 1745 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1746 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1747 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1748 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1749 }; 1750 1751 struct mlx5_ifc_nodnic_event_word_bits { 1752 u8 driver_reset_needed[0x1]; 1753 u8 port_management_change_event[0x1]; 1754 u8 reserved_0[0x19]; 1755 u8 link_type[0x1]; 1756 u8 port_state[0x4]; 1757 }; 1758 1759 struct mlx5_ifc_nic_vport_change_event_bits { 1760 u8 reserved_0[0x10]; 1761 u8 vport_num[0x10]; 1762 1763 u8 reserved_1[0xc0]; 1764 }; 1765 1766 struct mlx5_ifc_pages_req_event_bits { 1767 u8 reserved_0[0x10]; 1768 u8 function_id[0x10]; 1769 1770 u8 num_pages[0x20]; 1771 1772 u8 reserved_1[0xa0]; 1773 }; 1774 1775 struct mlx5_ifc_cmd_inter_comp_event_bits { 1776 u8 command_completion_vector[0x20]; 1777 1778 u8 reserved_0[0xc0]; 1779 }; 1780 1781 struct mlx5_ifc_stall_vl_event_bits { 1782 u8 reserved_0[0x18]; 1783 u8 port_num[0x1]; 1784 u8 reserved_1[0x3]; 1785 u8 vl[0x4]; 1786 1787 u8 reserved_2[0xa0]; 1788 }; 1789 1790 struct mlx5_ifc_db_bf_congestion_event_bits { 1791 u8 event_subtype[0x8]; 1792 u8 reserved_0[0x8]; 1793 u8 congestion_level[0x8]; 1794 u8 reserved_1[0x8]; 1795 1796 u8 reserved_2[0xa0]; 1797 }; 1798 1799 struct mlx5_ifc_gpio_event_bits { 1800 u8 reserved_0[0x60]; 1801 1802 u8 gpio_event_hi[0x20]; 1803 1804 u8 gpio_event_lo[0x20]; 1805 1806 u8 reserved_1[0x40]; 1807 }; 1808 1809 struct mlx5_ifc_port_state_change_event_bits { 1810 u8 reserved_0[0x40]; 1811 1812 u8 port_num[0x4]; 1813 u8 reserved_1[0x1c]; 1814 1815 u8 reserved_2[0x80]; 1816 }; 1817 1818 struct mlx5_ifc_dropped_packet_logged_bits { 1819 u8 reserved_0[0xe0]; 1820 }; 1821 1822 enum { 1823 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1824 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1825 }; 1826 1827 struct mlx5_ifc_cq_error_bits { 1828 u8 reserved_0[0x8]; 1829 u8 cqn[0x18]; 1830 1831 u8 reserved_1[0x20]; 1832 1833 u8 reserved_2[0x18]; 1834 u8 syndrome[0x8]; 1835 1836 u8 reserved_3[0x80]; 1837 }; 1838 1839 struct mlx5_ifc_rdma_page_fault_event_bits { 1840 u8 bytes_commited[0x20]; 1841 1842 u8 r_key[0x20]; 1843 1844 u8 reserved_0[0x10]; 1845 u8 packet_len[0x10]; 1846 1847 u8 rdma_op_len[0x20]; 1848 1849 u8 rdma_va[0x40]; 1850 1851 u8 reserved_1[0x5]; 1852 u8 rdma[0x1]; 1853 u8 write[0x1]; 1854 u8 requestor[0x1]; 1855 u8 qp_number[0x18]; 1856 }; 1857 1858 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1859 u8 bytes_committed[0x20]; 1860 1861 u8 reserved_0[0x10]; 1862 u8 wqe_index[0x10]; 1863 1864 u8 reserved_1[0x10]; 1865 u8 len[0x10]; 1866 1867 u8 reserved_2[0x60]; 1868 1869 u8 reserved_3[0x5]; 1870 u8 rdma[0x1]; 1871 u8 write_read[0x1]; 1872 u8 requestor[0x1]; 1873 u8 qpn[0x18]; 1874 }; 1875 1876 enum { 1877 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1878 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1879 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1880 }; 1881 1882 struct mlx5_ifc_qp_events_bits { 1883 u8 reserved_0[0xa0]; 1884 1885 u8 type[0x8]; 1886 u8 reserved_1[0x18]; 1887 1888 u8 reserved_2[0x8]; 1889 u8 qpn_rqn_sqn[0x18]; 1890 }; 1891 1892 struct mlx5_ifc_dct_events_bits { 1893 u8 reserved_0[0xc0]; 1894 1895 u8 reserved_1[0x8]; 1896 u8 dct_number[0x18]; 1897 }; 1898 1899 struct mlx5_ifc_comp_event_bits { 1900 u8 reserved_0[0xc0]; 1901 1902 u8 reserved_1[0x8]; 1903 u8 cq_number[0x18]; 1904 }; 1905 1906 struct mlx5_ifc_fw_version_bits { 1907 u8 major[0x10]; 1908 u8 reserved_0[0x10]; 1909 1910 u8 minor[0x10]; 1911 u8 subminor[0x10]; 1912 1913 u8 second[0x8]; 1914 u8 minute[0x8]; 1915 u8 hour[0x8]; 1916 u8 reserved_1[0x8]; 1917 1918 u8 year[0x10]; 1919 u8 month[0x8]; 1920 u8 day[0x8]; 1921 }; 1922 1923 enum { 1924 MLX5_QPC_STATE_RST = 0x0, 1925 MLX5_QPC_STATE_INIT = 0x1, 1926 MLX5_QPC_STATE_RTR = 0x2, 1927 MLX5_QPC_STATE_RTS = 0x3, 1928 MLX5_QPC_STATE_SQER = 0x4, 1929 MLX5_QPC_STATE_SQD = 0x5, 1930 MLX5_QPC_STATE_ERR = 0x6, 1931 MLX5_QPC_STATE_SUSPENDED = 0x9, 1932 }; 1933 1934 enum { 1935 MLX5_QPC_ST_RC = 0x0, 1936 MLX5_QPC_ST_UC = 0x1, 1937 MLX5_QPC_ST_UD = 0x2, 1938 MLX5_QPC_ST_XRC = 0x3, 1939 MLX5_QPC_ST_DCI = 0x5, 1940 MLX5_QPC_ST_QP0 = 0x7, 1941 MLX5_QPC_ST_QP1 = 0x8, 1942 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1943 MLX5_QPC_ST_REG_UMR = 0xc, 1944 }; 1945 1946 enum { 1947 MLX5_QP_PM_ARMED = 0x0, 1948 MLX5_QP_PM_REARM = 0x1, 1949 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1950 MLX5_QP_PM_MIGRATED = 0x3, 1951 }; 1952 1953 enum { 1954 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1955 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1956 }; 1957 1958 enum { 1959 MLX5_QPC_MTU_256_BYTES = 0x1, 1960 MLX5_QPC_MTU_512_BYTES = 0x2, 1961 MLX5_QPC_MTU_1K_BYTES = 0x3, 1962 MLX5_QPC_MTU_2K_BYTES = 0x4, 1963 MLX5_QPC_MTU_4K_BYTES = 0x5, 1964 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1965 }; 1966 1967 enum { 1968 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1969 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1970 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1971 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1972 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1973 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1974 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1975 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1976 }; 1977 1978 enum { 1979 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1980 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1981 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1982 }; 1983 1984 enum { 1985 MLX5_QPC_CS_RES_DISABLE = 0x0, 1986 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1987 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1988 }; 1989 1990 enum { 1991 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 1992 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 1993 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 1994 }; 1995 1996 struct mlx5_ifc_qpc_bits { 1997 u8 state[0x4]; 1998 u8 lag_tx_port_affinity[0x4]; 1999 u8 st[0x8]; 2000 u8 reserved_1[0x3]; 2001 u8 pm_state[0x2]; 2002 u8 reserved_2[0x7]; 2003 u8 end_padding_mode[0x2]; 2004 u8 reserved_3[0x2]; 2005 2006 u8 wq_signature[0x1]; 2007 u8 block_lb_mc[0x1]; 2008 u8 atomic_like_write_en[0x1]; 2009 u8 latency_sensitive[0x1]; 2010 u8 reserved_4[0x1]; 2011 u8 drain_sigerr[0x1]; 2012 u8 reserved_5[0x2]; 2013 u8 pd[0x18]; 2014 2015 u8 mtu[0x3]; 2016 u8 log_msg_max[0x5]; 2017 u8 reserved_6[0x1]; 2018 u8 log_rq_size[0x4]; 2019 u8 log_rq_stride[0x3]; 2020 u8 no_sq[0x1]; 2021 u8 log_sq_size[0x4]; 2022 u8 reserved_at_55[0x3]; 2023 u8 ts_format[0x2]; 2024 u8 reserved_at_5a[0x1]; 2025 u8 rlky[0x1]; 2026 u8 ulp_stateless_offload_mode[0x4]; 2027 2028 u8 counter_set_id[0x8]; 2029 u8 uar_page[0x18]; 2030 2031 u8 reserved_8[0x8]; 2032 u8 user_index[0x18]; 2033 2034 u8 reserved_9[0x3]; 2035 u8 log_page_size[0x5]; 2036 u8 remote_qpn[0x18]; 2037 2038 struct mlx5_ifc_ads_bits primary_address_path; 2039 2040 struct mlx5_ifc_ads_bits secondary_address_path; 2041 2042 u8 log_ack_req_freq[0x4]; 2043 u8 reserved_10[0x4]; 2044 u8 log_sra_max[0x3]; 2045 u8 reserved_11[0x2]; 2046 u8 retry_count[0x3]; 2047 u8 rnr_retry[0x3]; 2048 u8 reserved_12[0x1]; 2049 u8 fre[0x1]; 2050 u8 cur_rnr_retry[0x3]; 2051 u8 cur_retry_count[0x3]; 2052 u8 reserved_13[0x5]; 2053 2054 u8 reserved_14[0x20]; 2055 2056 u8 reserved_15[0x8]; 2057 u8 next_send_psn[0x18]; 2058 2059 u8 reserved_16[0x8]; 2060 u8 cqn_snd[0x18]; 2061 2062 u8 reserved_at_400[0x8]; 2063 2064 u8 deth_sqpn[0x18]; 2065 u8 reserved_17[0x20]; 2066 2067 u8 reserved_18[0x8]; 2068 u8 last_acked_psn[0x18]; 2069 2070 u8 reserved_19[0x8]; 2071 u8 ssn[0x18]; 2072 2073 u8 reserved_20[0x8]; 2074 u8 log_rra_max[0x3]; 2075 u8 reserved_21[0x1]; 2076 u8 atomic_mode[0x4]; 2077 u8 rre[0x1]; 2078 u8 rwe[0x1]; 2079 u8 rae[0x1]; 2080 u8 reserved_22[0x1]; 2081 u8 page_offset[0x6]; 2082 u8 reserved_23[0x3]; 2083 u8 cd_slave_receive[0x1]; 2084 u8 cd_slave_send[0x1]; 2085 u8 cd_master[0x1]; 2086 2087 u8 reserved_24[0x3]; 2088 u8 min_rnr_nak[0x5]; 2089 u8 next_rcv_psn[0x18]; 2090 2091 u8 reserved_25[0x8]; 2092 u8 xrcd[0x18]; 2093 2094 u8 reserved_26[0x8]; 2095 u8 cqn_rcv[0x18]; 2096 2097 u8 dbr_addr[0x40]; 2098 2099 u8 q_key[0x20]; 2100 2101 u8 reserved_27[0x5]; 2102 u8 rq_type[0x3]; 2103 u8 srqn_rmpn[0x18]; 2104 2105 u8 reserved_28[0x8]; 2106 u8 rmsn[0x18]; 2107 2108 u8 hw_sq_wqebb_counter[0x10]; 2109 u8 sw_sq_wqebb_counter[0x10]; 2110 2111 u8 hw_rq_counter[0x20]; 2112 2113 u8 sw_rq_counter[0x20]; 2114 2115 u8 reserved_29[0x20]; 2116 2117 u8 reserved_30[0xf]; 2118 u8 cgs[0x1]; 2119 u8 cs_req[0x8]; 2120 u8 cs_res[0x8]; 2121 2122 u8 dc_access_key[0x40]; 2123 2124 u8 rdma_active[0x1]; 2125 u8 comm_est[0x1]; 2126 u8 suspended[0x1]; 2127 u8 reserved_31[0x5]; 2128 u8 send_msg_psn[0x18]; 2129 2130 u8 reserved_32[0x8]; 2131 u8 rcv_msg_psn[0x18]; 2132 2133 u8 rdma_va[0x40]; 2134 2135 u8 rdma_key[0x20]; 2136 2137 u8 reserved_33[0x20]; 2138 }; 2139 2140 struct mlx5_ifc_roce_addr_layout_bits { 2141 u8 source_l3_address[16][0x8]; 2142 2143 u8 reserved_0[0x3]; 2144 u8 vlan_valid[0x1]; 2145 u8 vlan_id[0xc]; 2146 u8 source_mac_47_32[0x10]; 2147 2148 u8 source_mac_31_0[0x20]; 2149 2150 u8 reserved_1[0x14]; 2151 u8 roce_l3_type[0x4]; 2152 u8 roce_version[0x8]; 2153 2154 u8 reserved_2[0x20]; 2155 }; 2156 2157 struct mlx5_ifc_rdbc_bits { 2158 u8 reserved_0[0x1c]; 2159 u8 type[0x4]; 2160 2161 u8 reserved_1[0x20]; 2162 2163 u8 reserved_2[0x8]; 2164 u8 psn[0x18]; 2165 2166 u8 rkey[0x20]; 2167 2168 u8 address[0x40]; 2169 2170 u8 byte_count[0x20]; 2171 2172 u8 reserved_3[0x20]; 2173 2174 u8 atomic_resp[32][0x8]; 2175 }; 2176 2177 enum { 2178 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2179 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2180 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2181 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2182 }; 2183 2184 struct mlx5_ifc_flow_context_bits { 2185 u8 reserved_0[0x20]; 2186 2187 u8 group_id[0x20]; 2188 2189 u8 reserved_1[0x8]; 2190 u8 flow_tag[0x18]; 2191 2192 u8 reserved_2[0x10]; 2193 u8 action[0x10]; 2194 2195 u8 reserved_3[0x8]; 2196 u8 destination_list_size[0x18]; 2197 2198 u8 reserved_4[0x8]; 2199 u8 flow_counter_list_size[0x18]; 2200 2201 u8 reserved_5[0x140]; 2202 2203 struct mlx5_ifc_fte_match_param_bits match_value; 2204 2205 u8 reserved_6[0x600]; 2206 2207 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2208 }; 2209 2210 enum { 2211 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2212 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2213 }; 2214 2215 struct mlx5_ifc_xrc_srqc_bits { 2216 u8 state[0x4]; 2217 u8 log_xrc_srq_size[0x4]; 2218 u8 reserved_0[0x18]; 2219 2220 u8 wq_signature[0x1]; 2221 u8 cont_srq[0x1]; 2222 u8 reserved_1[0x1]; 2223 u8 rlky[0x1]; 2224 u8 basic_cyclic_rcv_wqe[0x1]; 2225 u8 log_rq_stride[0x3]; 2226 u8 xrcd[0x18]; 2227 2228 u8 page_offset[0x6]; 2229 u8 reserved_2[0x2]; 2230 u8 cqn[0x18]; 2231 2232 u8 reserved_3[0x20]; 2233 2234 u8 reserved_4[0x2]; 2235 u8 log_page_size[0x6]; 2236 u8 user_index[0x18]; 2237 2238 u8 reserved_5[0x20]; 2239 2240 u8 reserved_6[0x8]; 2241 u8 pd[0x18]; 2242 2243 u8 lwm[0x10]; 2244 u8 wqe_cnt[0x10]; 2245 2246 u8 reserved_7[0x40]; 2247 2248 u8 db_record_addr_h[0x20]; 2249 2250 u8 db_record_addr_l[0x1e]; 2251 u8 reserved_8[0x2]; 2252 2253 u8 reserved_9[0x80]; 2254 }; 2255 2256 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2257 u8 counter_error_queues[0x20]; 2258 2259 u8 total_error_queues[0x20]; 2260 2261 u8 send_queue_priority_update_flow[0x20]; 2262 2263 u8 reserved_at_60[0x20]; 2264 2265 u8 nic_receive_steering_discard[0x40]; 2266 2267 u8 receive_discard_vport_down[0x40]; 2268 2269 u8 transmit_discard_vport_down[0x40]; 2270 2271 u8 reserved_at_140[0xec0]; 2272 }; 2273 2274 struct mlx5_ifc_traffic_counter_bits { 2275 u8 packets[0x40]; 2276 2277 u8 octets[0x40]; 2278 }; 2279 2280 struct mlx5_ifc_tisc_bits { 2281 u8 strict_lag_tx_port_affinity[0x1]; 2282 u8 tls_en[0x1]; 2283 u8 reserved_at_2[0x2]; 2284 u8 lag_tx_port_affinity[0x04]; 2285 2286 u8 reserved_at_8[0x4]; 2287 u8 prio[0x4]; 2288 u8 reserved_1[0x10]; 2289 2290 u8 reserved_2[0x100]; 2291 2292 u8 reserved_3[0x8]; 2293 u8 transport_domain[0x18]; 2294 2295 u8 reserved_4[0x8]; 2296 u8 underlay_qpn[0x18]; 2297 2298 u8 reserved_5[0x8]; 2299 u8 pd[0x18]; 2300 2301 u8 reserved_6[0x380]; 2302 }; 2303 2304 enum { 2305 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2306 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2307 }; 2308 2309 enum { 2310 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2311 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2312 }; 2313 2314 enum { 2315 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2316 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2317 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2318 }; 2319 2320 enum { 2321 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2322 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2323 }; 2324 2325 struct mlx5_ifc_tirc_bits { 2326 u8 reserved_0[0x20]; 2327 2328 u8 disp_type[0x4]; 2329 u8 tls_en[0x1]; 2330 u8 reserved_at_25[0x1b]; 2331 2332 u8 reserved_2[0x40]; 2333 2334 u8 reserved_3[0x4]; 2335 u8 lro_timeout_period_usecs[0x10]; 2336 u8 lro_enable_mask[0x4]; 2337 u8 lro_max_msg_sz[0x8]; 2338 2339 u8 reserved_4[0x40]; 2340 2341 u8 reserved_5[0x8]; 2342 u8 inline_rqn[0x18]; 2343 2344 u8 rx_hash_symmetric[0x1]; 2345 u8 reserved_6[0x1]; 2346 u8 tunneled_offload_en[0x1]; 2347 u8 reserved_7[0x5]; 2348 u8 indirect_table[0x18]; 2349 2350 u8 rx_hash_fn[0x4]; 2351 u8 reserved_8[0x2]; 2352 u8 self_lb_en[0x2]; 2353 u8 transport_domain[0x18]; 2354 2355 u8 rx_hash_toeplitz_key[10][0x20]; 2356 2357 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2358 2359 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2360 2361 u8 reserved_9[0x4c0]; 2362 }; 2363 2364 enum { 2365 MLX5_SRQC_STATE_GOOD = 0x0, 2366 MLX5_SRQC_STATE_ERROR = 0x1, 2367 }; 2368 2369 struct mlx5_ifc_srqc_bits { 2370 u8 state[0x4]; 2371 u8 log_srq_size[0x4]; 2372 u8 reserved_0[0x18]; 2373 2374 u8 wq_signature[0x1]; 2375 u8 cont_srq[0x1]; 2376 u8 reserved_1[0x1]; 2377 u8 rlky[0x1]; 2378 u8 reserved_2[0x1]; 2379 u8 log_rq_stride[0x3]; 2380 u8 xrcd[0x18]; 2381 2382 u8 page_offset[0x6]; 2383 u8 reserved_3[0x2]; 2384 u8 cqn[0x18]; 2385 2386 u8 reserved_4[0x20]; 2387 2388 u8 reserved_5[0x2]; 2389 u8 log_page_size[0x6]; 2390 u8 reserved_6[0x18]; 2391 2392 u8 reserved_7[0x20]; 2393 2394 u8 reserved_8[0x8]; 2395 u8 pd[0x18]; 2396 2397 u8 lwm[0x10]; 2398 u8 wqe_cnt[0x10]; 2399 2400 u8 reserved_9[0x40]; 2401 2402 u8 dbr_addr[0x40]; 2403 2404 u8 reserved_10[0x80]; 2405 }; 2406 2407 enum { 2408 MLX5_SQC_STATE_RST = 0x0, 2409 MLX5_SQC_STATE_RDY = 0x1, 2410 MLX5_SQC_STATE_ERR = 0x3, 2411 }; 2412 2413 enum { 2414 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2415 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2416 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2417 }; 2418 2419 struct mlx5_ifc_sqc_bits { 2420 u8 rlkey[0x1]; 2421 u8 cd_master[0x1]; 2422 u8 fre[0x1]; 2423 u8 flush_in_error_en[0x1]; 2424 u8 allow_multi_pkt_send_wqe[0x1]; 2425 u8 min_wqe_inline_mode[0x3]; 2426 u8 state[0x4]; 2427 u8 reg_umr[0x1]; 2428 u8 allow_swp[0x1]; 2429 u8 reserved_at_e[0x4]; 2430 u8 qos_remap_en[0x1]; 2431 u8 reserved_at_d[0x7]; 2432 u8 ts_format[0x2]; 2433 u8 reserved_at_1c[0x4]; 2434 2435 u8 reserved_1[0x8]; 2436 u8 user_index[0x18]; 2437 2438 u8 reserved_2[0x8]; 2439 u8 cqn[0x18]; 2440 2441 u8 reserved_3[0x80]; 2442 2443 u8 qos_para_vport_number[0x10]; 2444 u8 packet_pacing_rate_limit_index[0x10]; 2445 2446 u8 tis_lst_sz[0x10]; 2447 u8 qos_queue_group_id[0x10]; 2448 2449 u8 reserved_4[0x8]; 2450 u8 queue_handle[0x18]; 2451 2452 u8 reserved_5[0x20]; 2453 2454 u8 reserved_6[0x8]; 2455 u8 tis_num_0[0x18]; 2456 2457 struct mlx5_ifc_wq_bits wq; 2458 }; 2459 2460 struct mlx5_ifc_query_pp_rate_limit_in_bits { 2461 u8 opcode[0x10]; 2462 u8 uid[0x10]; 2463 2464 u8 reserved1[0x10]; 2465 u8 op_mod[0x10]; 2466 2467 u8 reserved2[0x10]; 2468 u8 rate_limit_index[0x10]; 2469 2470 u8 reserved_3[0x20]; 2471 }; 2472 2473 struct mlx5_ifc_pp_context_bits { 2474 u8 rate_limit[0x20]; 2475 2476 u8 burst_upper_bound[0x20]; 2477 2478 u8 reserved_1[0xc]; 2479 u8 rate_mode[0x4]; 2480 u8 typical_packet_size[0x10]; 2481 2482 u8 reserved_2[0x8]; 2483 u8 qos_handle[0x18]; 2484 2485 u8 reserved_3[0x40]; 2486 }; 2487 2488 struct mlx5_ifc_query_pp_rate_limit_out_bits { 2489 u8 status[0x8]; 2490 u8 reserved_1[0x18]; 2491 2492 u8 syndrome[0x20]; 2493 2494 u8 reserved_2[0x40]; 2495 2496 struct mlx5_ifc_pp_context_bits pp_context; 2497 }; 2498 2499 enum { 2500 MLX5_TSAR_TYPE_DWRR = 0, 2501 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2502 MLX5_TSAR_TYPE_ETS = 2 2503 }; 2504 2505 struct mlx5_ifc_tsar_element_attributes_bits { 2506 u8 reserved_0[0x8]; 2507 u8 tsar_type[0x8]; 2508 u8 reserved_1[0x10]; 2509 }; 2510 2511 struct mlx5_ifc_vport_element_attributes_bits { 2512 u8 reserved_0[0x10]; 2513 u8 vport_number[0x10]; 2514 }; 2515 2516 struct mlx5_ifc_vport_tc_element_attributes_bits { 2517 u8 traffic_class[0x10]; 2518 u8 vport_number[0x10]; 2519 }; 2520 2521 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2522 u8 reserved_0[0x0C]; 2523 u8 traffic_class[0x04]; 2524 u8 qos_para_vport_number[0x10]; 2525 }; 2526 2527 enum { 2528 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2529 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2530 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2531 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2532 }; 2533 2534 struct mlx5_ifc_scheduling_context_bits { 2535 u8 element_type[0x8]; 2536 u8 reserved_at_8[0x18]; 2537 2538 u8 element_attributes[0x20]; 2539 2540 u8 parent_element_id[0x20]; 2541 2542 u8 reserved_at_60[0x40]; 2543 2544 u8 bw_share[0x20]; 2545 2546 u8 max_average_bw[0x20]; 2547 2548 u8 reserved_at_e0[0x120]; 2549 }; 2550 2551 struct mlx5_ifc_rqtc_bits { 2552 u8 reserved_0[0xa0]; 2553 2554 u8 reserved_1[0x10]; 2555 u8 rqt_max_size[0x10]; 2556 2557 u8 reserved_2[0x10]; 2558 u8 rqt_actual_size[0x10]; 2559 2560 u8 reserved_3[0x6a0]; 2561 2562 struct mlx5_ifc_rq_num_bits rq_num[0]; 2563 }; 2564 2565 enum { 2566 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2567 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2568 }; 2569 2570 enum { 2571 MLX5_RQC_STATE_RST = 0x0, 2572 MLX5_RQC_STATE_RDY = 0x1, 2573 MLX5_RQC_STATE_ERR = 0x3, 2574 }; 2575 2576 enum { 2577 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2578 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2579 }; 2580 2581 enum { 2582 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2583 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2584 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2585 }; 2586 2587 struct mlx5_ifc_rqc_bits { 2588 u8 rlkey[0x1]; 2589 u8 delay_drop_en[0x1]; 2590 u8 scatter_fcs[0x1]; 2591 u8 vlan_strip_disable[0x1]; 2592 u8 mem_rq_type[0x4]; 2593 u8 state[0x4]; 2594 u8 reserved_1[0x1]; 2595 u8 flush_in_error_en[0x1]; 2596 u8 reserved_at_e[0xc]; 2597 u8 ts_format[0x2]; 2598 u8 reserved_at_1c[0x4]; 2599 2600 u8 reserved_3[0x8]; 2601 u8 user_index[0x18]; 2602 2603 u8 reserved_4[0x8]; 2604 u8 cqn[0x18]; 2605 2606 u8 counter_set_id[0x8]; 2607 u8 reserved_5[0x18]; 2608 2609 u8 reserved_6[0x8]; 2610 u8 rmpn[0x18]; 2611 2612 u8 reserved_7[0xe0]; 2613 2614 struct mlx5_ifc_wq_bits wq; 2615 }; 2616 2617 enum { 2618 MLX5_RMPC_STATE_RDY = 0x1, 2619 MLX5_RMPC_STATE_ERR = 0x3, 2620 }; 2621 2622 struct mlx5_ifc_rmpc_bits { 2623 u8 reserved_0[0x8]; 2624 u8 state[0x4]; 2625 u8 reserved_1[0x14]; 2626 2627 u8 basic_cyclic_rcv_wqe[0x1]; 2628 u8 reserved_2[0x1f]; 2629 2630 u8 reserved_3[0x140]; 2631 2632 struct mlx5_ifc_wq_bits wq; 2633 }; 2634 2635 enum { 2636 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2637 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2638 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2639 }; 2640 2641 struct mlx5_ifc_nic_vport_context_bits { 2642 u8 reserved_0[0x5]; 2643 u8 min_wqe_inline_mode[0x3]; 2644 u8 reserved_1[0x15]; 2645 u8 disable_mc_local_lb[0x1]; 2646 u8 disable_uc_local_lb[0x1]; 2647 u8 roce_en[0x1]; 2648 2649 u8 arm_change_event[0x1]; 2650 u8 reserved_2[0x1a]; 2651 u8 event_on_mtu[0x1]; 2652 u8 event_on_promisc_change[0x1]; 2653 u8 event_on_vlan_change[0x1]; 2654 u8 event_on_mc_address_change[0x1]; 2655 u8 event_on_uc_address_change[0x1]; 2656 2657 u8 reserved_3[0xe0]; 2658 2659 u8 reserved_4[0x10]; 2660 u8 mtu[0x10]; 2661 2662 u8 system_image_guid[0x40]; 2663 2664 u8 port_guid[0x40]; 2665 2666 u8 node_guid[0x40]; 2667 2668 u8 reserved_5[0x140]; 2669 2670 u8 qkey_violation_counter[0x10]; 2671 u8 reserved_6[0x10]; 2672 2673 u8 reserved_7[0x420]; 2674 2675 u8 promisc_uc[0x1]; 2676 u8 promisc_mc[0x1]; 2677 u8 promisc_all[0x1]; 2678 u8 reserved_8[0x2]; 2679 u8 allowed_list_type[0x3]; 2680 u8 reserved_9[0xc]; 2681 u8 allowed_list_size[0xc]; 2682 2683 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2684 2685 u8 reserved_10[0x20]; 2686 2687 u8 current_uc_mac_address[0][0x40]; 2688 }; 2689 2690 enum { 2691 MLX5_ACCESS_MODE_PA = 0x0, 2692 MLX5_ACCESS_MODE_MTT = 0x1, 2693 MLX5_ACCESS_MODE_KLM = 0x2, 2694 }; 2695 2696 struct mlx5_ifc_mkc_bits { 2697 u8 reserved_at_0[0x1]; 2698 u8 free[0x1]; 2699 u8 reserved_at_2[0x1]; 2700 u8 access_mode_4_2[0x3]; 2701 u8 reserved_at_6[0x7]; 2702 u8 relaxed_ordering_write[0x1]; 2703 u8 reserved_at_e[0x1]; 2704 u8 small_fence_on_rdma_read_response[0x1]; 2705 u8 umr_en[0x1]; 2706 u8 a[0x1]; 2707 u8 rw[0x1]; 2708 u8 rr[0x1]; 2709 u8 lw[0x1]; 2710 u8 lr[0x1]; 2711 u8 access_mode[0x2]; 2712 u8 reserved_2[0x8]; 2713 2714 u8 qpn[0x18]; 2715 u8 mkey_7_0[0x8]; 2716 2717 u8 reserved_3[0x20]; 2718 2719 u8 length64[0x1]; 2720 u8 bsf_en[0x1]; 2721 u8 sync_umr[0x1]; 2722 u8 reserved_4[0x2]; 2723 u8 expected_sigerr_count[0x1]; 2724 u8 reserved_5[0x1]; 2725 u8 en_rinval[0x1]; 2726 u8 pd[0x18]; 2727 2728 u8 start_addr[0x40]; 2729 2730 u8 len[0x40]; 2731 2732 u8 bsf_octword_size[0x20]; 2733 2734 u8 reserved_6[0x80]; 2735 2736 u8 translations_octword_size[0x20]; 2737 2738 u8 reserved_at_1c0[0x19]; 2739 u8 relaxed_ordering_read[0x1]; 2740 u8 reserved_at_1d9[0x1]; 2741 u8 log_page_size[0x5]; 2742 2743 u8 reserved_8[0x20]; 2744 }; 2745 2746 struct mlx5_ifc_pkey_bits { 2747 u8 reserved_0[0x10]; 2748 u8 pkey[0x10]; 2749 }; 2750 2751 struct mlx5_ifc_array128_auto_bits { 2752 u8 array128_auto[16][0x8]; 2753 }; 2754 2755 enum { 2756 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2757 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2758 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2759 }; 2760 2761 enum { 2762 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2763 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2764 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2765 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2766 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2767 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2768 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2769 }; 2770 2771 enum { 2772 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2773 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2774 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2775 }; 2776 2777 enum { 2778 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2779 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2780 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2781 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2782 }; 2783 2784 enum { 2785 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2786 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2787 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2788 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2789 }; 2790 2791 struct mlx5_ifc_hca_vport_context_bits { 2792 u8 field_select[0x20]; 2793 2794 u8 reserved_0[0xe0]; 2795 2796 u8 sm_virt_aware[0x1]; 2797 u8 has_smi[0x1]; 2798 u8 has_raw[0x1]; 2799 u8 grh_required[0x1]; 2800 u8 reserved_1[0x1]; 2801 u8 min_wqe_inline_mode[0x3]; 2802 u8 reserved_2[0x8]; 2803 u8 port_physical_state[0x4]; 2804 u8 vport_state_policy[0x4]; 2805 u8 port_state[0x4]; 2806 u8 vport_state[0x4]; 2807 2808 u8 reserved_3[0x20]; 2809 2810 u8 system_image_guid[0x40]; 2811 2812 u8 port_guid[0x40]; 2813 2814 u8 node_guid[0x40]; 2815 2816 u8 cap_mask1[0x20]; 2817 2818 u8 cap_mask1_field_select[0x20]; 2819 2820 u8 cap_mask2[0x20]; 2821 2822 u8 cap_mask2_field_select[0x20]; 2823 2824 u8 reserved_4[0x80]; 2825 2826 u8 lid[0x10]; 2827 u8 reserved_5[0x4]; 2828 u8 init_type_reply[0x4]; 2829 u8 lmc[0x3]; 2830 u8 subnet_timeout[0x5]; 2831 2832 u8 sm_lid[0x10]; 2833 u8 sm_sl[0x4]; 2834 u8 reserved_6[0xc]; 2835 2836 u8 qkey_violation_counter[0x10]; 2837 u8 pkey_violation_counter[0x10]; 2838 2839 u8 reserved_7[0xca0]; 2840 }; 2841 2842 union mlx5_ifc_hca_cap_union_bits { 2843 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2844 struct mlx5_ifc_odp_cap_bits odp_cap; 2845 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2846 struct mlx5_ifc_roce_cap_bits roce_cap; 2847 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2848 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2849 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2850 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2851 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2852 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2853 struct mlx5_ifc_qos_cap_bits qos_cap; 2854 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 2855 u8 reserved_0[0x8000]; 2856 }; 2857 2858 enum { 2859 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2860 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2861 }; 2862 2863 struct mlx5_ifc_flow_table_context_bits { 2864 u8 encap_en[0x1]; 2865 u8 decap_en[0x1]; 2866 u8 reserved_at_2[0x2]; 2867 u8 table_miss_action[0x4]; 2868 u8 level[0x8]; 2869 u8 reserved_at_10[0x8]; 2870 u8 log_size[0x8]; 2871 2872 u8 reserved_at_20[0x8]; 2873 u8 table_miss_id[0x18]; 2874 2875 u8 reserved_at_40[0x8]; 2876 u8 lag_master_next_table_id[0x18]; 2877 2878 u8 reserved_at_60[0xe0]; 2879 }; 2880 2881 struct mlx5_ifc_esw_vport_context_bits { 2882 u8 reserved_0[0x3]; 2883 u8 vport_svlan_strip[0x1]; 2884 u8 vport_cvlan_strip[0x1]; 2885 u8 vport_svlan_insert[0x1]; 2886 u8 vport_cvlan_insert[0x2]; 2887 u8 reserved_1[0x18]; 2888 2889 u8 reserved_2[0x20]; 2890 2891 u8 svlan_cfi[0x1]; 2892 u8 svlan_pcp[0x3]; 2893 u8 svlan_id[0xc]; 2894 u8 cvlan_cfi[0x1]; 2895 u8 cvlan_pcp[0x3]; 2896 u8 cvlan_id[0xc]; 2897 2898 u8 reserved_3[0x7a0]; 2899 }; 2900 2901 enum { 2902 MLX5_EQC_STATUS_OK = 0x0, 2903 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2904 }; 2905 2906 enum { 2907 MLX5_EQ_STATE_ARMED = 0x9, 2908 MLX5_EQ_STATE_FIRED = 0xa, 2909 }; 2910 2911 struct mlx5_ifc_eqc_bits { 2912 u8 status[0x4]; 2913 u8 reserved_0[0x9]; 2914 u8 ec[0x1]; 2915 u8 oi[0x1]; 2916 u8 reserved_1[0x5]; 2917 u8 st[0x4]; 2918 u8 reserved_2[0x8]; 2919 2920 u8 reserved_3[0x20]; 2921 2922 u8 reserved_4[0x14]; 2923 u8 page_offset[0x6]; 2924 u8 reserved_5[0x6]; 2925 2926 u8 reserved_6[0x3]; 2927 u8 log_eq_size[0x5]; 2928 u8 uar_page[0x18]; 2929 2930 u8 reserved_7[0x20]; 2931 2932 u8 reserved_8[0x18]; 2933 u8 intr[0x8]; 2934 2935 u8 reserved_9[0x3]; 2936 u8 log_page_size[0x5]; 2937 u8 reserved_10[0x18]; 2938 2939 u8 reserved_11[0x60]; 2940 2941 u8 reserved_12[0x8]; 2942 u8 consumer_counter[0x18]; 2943 2944 u8 reserved_13[0x8]; 2945 u8 producer_counter[0x18]; 2946 2947 u8 reserved_14[0x80]; 2948 }; 2949 2950 enum { 2951 MLX5_DCTC_STATE_ACTIVE = 0x0, 2952 MLX5_DCTC_STATE_DRAINING = 0x1, 2953 MLX5_DCTC_STATE_DRAINED = 0x2, 2954 }; 2955 2956 enum { 2957 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2958 MLX5_DCTC_CS_RES_NA = 0x1, 2959 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2960 }; 2961 2962 enum { 2963 MLX5_DCTC_MTU_256_BYTES = 0x1, 2964 MLX5_DCTC_MTU_512_BYTES = 0x2, 2965 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2966 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2967 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2968 }; 2969 2970 struct mlx5_ifc_dctc_bits { 2971 u8 reserved_0[0x4]; 2972 u8 state[0x4]; 2973 u8 reserved_1[0x18]; 2974 2975 u8 reserved_2[0x8]; 2976 u8 user_index[0x18]; 2977 2978 u8 reserved_3[0x8]; 2979 u8 cqn[0x18]; 2980 2981 u8 counter_set_id[0x8]; 2982 u8 atomic_mode[0x4]; 2983 u8 rre[0x1]; 2984 u8 rwe[0x1]; 2985 u8 rae[0x1]; 2986 u8 atomic_like_write_en[0x1]; 2987 u8 latency_sensitive[0x1]; 2988 u8 rlky[0x1]; 2989 u8 reserved_4[0xe]; 2990 2991 u8 reserved_5[0x8]; 2992 u8 cs_res[0x8]; 2993 u8 reserved_6[0x3]; 2994 u8 min_rnr_nak[0x5]; 2995 u8 reserved_7[0x8]; 2996 2997 u8 reserved_8[0x8]; 2998 u8 srqn[0x18]; 2999 3000 u8 reserved_9[0x8]; 3001 u8 pd[0x18]; 3002 3003 u8 tclass[0x8]; 3004 u8 reserved_10[0x4]; 3005 u8 flow_label[0x14]; 3006 3007 u8 dc_access_key[0x40]; 3008 3009 u8 reserved_11[0x5]; 3010 u8 mtu[0x3]; 3011 u8 port[0x8]; 3012 u8 pkey_index[0x10]; 3013 3014 u8 reserved_12[0x8]; 3015 u8 my_addr_index[0x8]; 3016 u8 reserved_13[0x8]; 3017 u8 hop_limit[0x8]; 3018 3019 u8 dc_access_key_violation_count[0x20]; 3020 3021 u8 reserved_14[0x14]; 3022 u8 dei_cfi[0x1]; 3023 u8 eth_prio[0x3]; 3024 u8 ecn[0x2]; 3025 u8 dscp[0x6]; 3026 3027 u8 reserved_15[0x40]; 3028 }; 3029 3030 enum { 3031 MLX5_CQC_STATUS_OK = 0x0, 3032 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3033 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3034 }; 3035 3036 enum { 3037 CQE_SIZE_64 = 0x0, 3038 CQE_SIZE_128 = 0x1, 3039 }; 3040 3041 enum { 3042 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3043 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3044 }; 3045 3046 enum { 3047 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 3048 MLX5_CQ_STATE_ARMED = 0x9, 3049 MLX5_CQ_STATE_FIRED = 0xa, 3050 }; 3051 3052 struct mlx5_ifc_cqc_bits { 3053 u8 status[0x4]; 3054 u8 reserved_0[0x4]; 3055 u8 cqe_sz[0x3]; 3056 u8 cc[0x1]; 3057 u8 reserved_1[0x1]; 3058 u8 scqe_break_moderation_en[0x1]; 3059 u8 oi[0x1]; 3060 u8 cq_period_mode[0x2]; 3061 u8 cqe_compression_en[0x1]; 3062 u8 mini_cqe_res_format[0x2]; 3063 u8 st[0x4]; 3064 u8 reserved_2[0x8]; 3065 3066 u8 reserved_3[0x20]; 3067 3068 u8 reserved_4[0x14]; 3069 u8 page_offset[0x6]; 3070 u8 reserved_5[0x6]; 3071 3072 u8 reserved_6[0x3]; 3073 u8 log_cq_size[0x5]; 3074 u8 uar_page[0x18]; 3075 3076 u8 reserved_7[0x4]; 3077 u8 cq_period[0xc]; 3078 u8 cq_max_count[0x10]; 3079 3080 u8 reserved_8[0x18]; 3081 u8 c_eqn[0x8]; 3082 3083 u8 reserved_9[0x3]; 3084 u8 log_page_size[0x5]; 3085 u8 reserved_10[0x18]; 3086 3087 u8 reserved_11[0x20]; 3088 3089 u8 reserved_12[0x8]; 3090 u8 last_notified_index[0x18]; 3091 3092 u8 reserved_13[0x8]; 3093 u8 last_solicit_index[0x18]; 3094 3095 u8 reserved_14[0x8]; 3096 u8 consumer_counter[0x18]; 3097 3098 u8 reserved_15[0x8]; 3099 u8 producer_counter[0x18]; 3100 3101 u8 reserved_16[0x40]; 3102 3103 u8 dbr_addr[0x40]; 3104 }; 3105 3106 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3107 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3108 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3109 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3110 u8 reserved_0[0x800]; 3111 }; 3112 3113 struct mlx5_ifc_query_adapter_param_block_bits { 3114 u8 reserved_0[0xc0]; 3115 3116 u8 reserved_1[0x8]; 3117 u8 ieee_vendor_id[0x18]; 3118 3119 u8 reserved_2[0x10]; 3120 u8 vsd_vendor_id[0x10]; 3121 3122 u8 vsd[208][0x8]; 3123 3124 u8 vsd_contd_psid[16][0x8]; 3125 }; 3126 3127 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3128 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3129 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3130 u8 reserved_0[0x20]; 3131 }; 3132 3133 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3134 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3135 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3136 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3137 u8 reserved_0[0x20]; 3138 }; 3139 3140 struct mlx5_ifc_bufferx_reg_bits { 3141 u8 reserved_0[0x6]; 3142 u8 lossy[0x1]; 3143 u8 epsb[0x1]; 3144 u8 reserved_1[0xc]; 3145 u8 size[0xc]; 3146 3147 u8 xoff_threshold[0x10]; 3148 u8 xon_threshold[0x10]; 3149 }; 3150 3151 struct mlx5_ifc_config_item_bits { 3152 u8 valid[0x2]; 3153 u8 reserved_0[0x2]; 3154 u8 header_type[0x2]; 3155 u8 reserved_1[0x2]; 3156 u8 default_location[0x1]; 3157 u8 reserved_2[0x7]; 3158 u8 version[0x4]; 3159 u8 reserved_3[0x3]; 3160 u8 length[0x9]; 3161 3162 u8 type[0x20]; 3163 3164 u8 reserved_4[0x10]; 3165 u8 crc16[0x10]; 3166 }; 3167 3168 struct mlx5_ifc_nodnic_port_config_reg_bits { 3169 struct mlx5_ifc_nodnic_event_word_bits event; 3170 3171 u8 network_en[0x1]; 3172 u8 dma_en[0x1]; 3173 u8 promisc_en[0x1]; 3174 u8 promisc_multicast_en[0x1]; 3175 u8 reserved_0[0x17]; 3176 u8 receive_filter_en[0x5]; 3177 3178 u8 reserved_1[0x10]; 3179 u8 mac_47_32[0x10]; 3180 3181 u8 mac_31_0[0x20]; 3182 3183 u8 receive_filters_mgid_mac[64][0x8]; 3184 3185 u8 gid[16][0x8]; 3186 3187 u8 reserved_2[0x10]; 3188 u8 lid[0x10]; 3189 3190 u8 reserved_3[0xc]; 3191 u8 sm_sl[0x4]; 3192 u8 sm_lid[0x10]; 3193 3194 u8 completion_address_63_32[0x20]; 3195 3196 u8 completion_address_31_12[0x14]; 3197 u8 reserved_4[0x6]; 3198 u8 log_cq_size[0x6]; 3199 3200 u8 working_buffer_address_63_32[0x20]; 3201 3202 u8 working_buffer_address_31_12[0x14]; 3203 u8 reserved_5[0xc]; 3204 3205 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3206 3207 u8 pkey_index[0x10]; 3208 u8 pkey[0x10]; 3209 3210 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3211 3212 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3213 3214 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3215 3216 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3217 3218 u8 reserved_6[0x400]; 3219 }; 3220 3221 union mlx5_ifc_event_auto_bits { 3222 struct mlx5_ifc_comp_event_bits comp_event; 3223 struct mlx5_ifc_dct_events_bits dct_events; 3224 struct mlx5_ifc_qp_events_bits qp_events; 3225 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3226 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3227 struct mlx5_ifc_cq_error_bits cq_error; 3228 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3229 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3230 struct mlx5_ifc_gpio_event_bits gpio_event; 3231 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3232 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3233 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3234 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3235 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3236 u8 reserved_0[0xe0]; 3237 }; 3238 3239 struct mlx5_ifc_health_buffer_bits { 3240 u8 reserved_0[0x100]; 3241 3242 u8 assert_existptr[0x20]; 3243 3244 u8 assert_callra[0x20]; 3245 3246 u8 reserved_1[0x40]; 3247 3248 u8 fw_version[0x20]; 3249 3250 u8 hw_id[0x20]; 3251 3252 u8 reserved_2[0x20]; 3253 3254 u8 irisc_index[0x8]; 3255 u8 synd[0x8]; 3256 u8 ext_synd[0x10]; 3257 }; 3258 3259 struct mlx5_ifc_register_loopback_control_bits { 3260 u8 no_lb[0x1]; 3261 u8 reserved_0[0x7]; 3262 u8 port[0x8]; 3263 u8 reserved_1[0x10]; 3264 3265 u8 reserved_2[0x60]; 3266 }; 3267 3268 struct mlx5_ifc_lrh_bits { 3269 u8 vl[4]; 3270 u8 lver[4]; 3271 u8 sl[4]; 3272 u8 reserved2[2]; 3273 u8 lnh[2]; 3274 u8 dlid[16]; 3275 u8 reserved5[5]; 3276 u8 pkt_len[11]; 3277 u8 slid[16]; 3278 }; 3279 3280 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3281 u8 reserved_0[0x40]; 3282 3283 u8 reserved_1[0x10]; 3284 u8 rol_mode[0x8]; 3285 u8 wol_mode[0x8]; 3286 }; 3287 3288 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3289 u8 reserved_0[0x40]; 3290 3291 u8 rol_mode_valid[0x1]; 3292 u8 wol_mode_valid[0x1]; 3293 u8 reserved_1[0xe]; 3294 u8 rol_mode[0x8]; 3295 u8 wol_mode[0x8]; 3296 3297 u8 reserved_2[0x7a0]; 3298 }; 3299 3300 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3301 u8 virtual_mac_en[0x1]; 3302 u8 mac_aux_v[0x1]; 3303 u8 reserved_0[0x1e]; 3304 3305 u8 reserved_1[0x40]; 3306 3307 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3308 3309 u8 reserved_2[0x760]; 3310 }; 3311 3312 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3313 u8 virtual_mac_en[0x1]; 3314 u8 mac_aux_v[0x1]; 3315 u8 reserved_0[0x1e]; 3316 3317 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3318 3319 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3320 3321 u8 reserved_1[0x760]; 3322 }; 3323 3324 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3325 struct mlx5_ifc_fw_version_bits fw_version; 3326 3327 u8 reserved_0[0x10]; 3328 u8 hash_signature[0x10]; 3329 3330 u8 psid[16][0x8]; 3331 3332 u8 reserved_1[0x6e0]; 3333 }; 3334 3335 struct mlx5_ifc_icmd_query_cap_in_bits { 3336 u8 reserved_0[0x10]; 3337 u8 capability_group[0x10]; 3338 }; 3339 3340 struct mlx5_ifc_icmd_query_cap_general_bits { 3341 u8 nv_access[0x1]; 3342 u8 fw_info_psid[0x1]; 3343 u8 reserved_0[0x1e]; 3344 3345 u8 reserved_1[0x16]; 3346 u8 rol_s[0x1]; 3347 u8 rol_g[0x1]; 3348 u8 reserved_2[0x1]; 3349 u8 wol_s[0x1]; 3350 u8 wol_g[0x1]; 3351 u8 wol_a[0x1]; 3352 u8 wol_b[0x1]; 3353 u8 wol_m[0x1]; 3354 u8 wol_u[0x1]; 3355 u8 wol_p[0x1]; 3356 }; 3357 3358 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3359 u8 status[0x8]; 3360 u8 reserved_0[0x18]; 3361 3362 u8 reserved_1[0x7e0]; 3363 }; 3364 3365 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3366 u8 status[0x8]; 3367 u8 reserved_0[0x18]; 3368 3369 u8 reserved_1[0x7e0]; 3370 }; 3371 3372 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3373 u8 address_hi[0x20]; 3374 3375 u8 address_lo[0x20]; 3376 3377 u8 reserved_0[0x7c0]; 3378 }; 3379 3380 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3381 u8 reserved_0[0x20]; 3382 3383 u8 address_hi[0x20]; 3384 3385 u8 address_lo[0x20]; 3386 3387 u8 reserved_1[0x7a0]; 3388 }; 3389 3390 struct mlx5_ifc_icmd_access_reg_out_bits { 3391 u8 reserved_0[0x11]; 3392 u8 status[0x7]; 3393 u8 reserved_1[0x8]; 3394 3395 u8 register_id[0x10]; 3396 u8 reserved_2[0x10]; 3397 3398 u8 reserved_3[0x40]; 3399 3400 u8 reserved_4[0x5]; 3401 u8 len[0xb]; 3402 u8 reserved_5[0x10]; 3403 3404 u8 register_data[0][0x20]; 3405 }; 3406 3407 enum { 3408 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3409 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3410 }; 3411 3412 struct mlx5_ifc_icmd_access_reg_in_bits { 3413 u8 constant_1[0x5]; 3414 u8 constant_2[0xb]; 3415 u8 reserved_0[0x10]; 3416 3417 u8 register_id[0x10]; 3418 u8 reserved_1[0x1]; 3419 u8 method[0x7]; 3420 u8 constant_3[0x8]; 3421 3422 u8 reserved_2[0x40]; 3423 3424 u8 constant_4[0x5]; 3425 u8 len[0xb]; 3426 u8 reserved_3[0x10]; 3427 3428 u8 register_data[0][0x20]; 3429 }; 3430 3431 enum { 3432 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3433 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3434 }; 3435 3436 struct mlx5_ifc_teardown_hca_out_bits { 3437 u8 status[0x8]; 3438 u8 reserved_0[0x18]; 3439 3440 u8 syndrome[0x20]; 3441 3442 u8 reserved_1[0x3f]; 3443 3444 u8 state[0x1]; 3445 }; 3446 3447 enum { 3448 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3449 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3450 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3451 }; 3452 3453 struct mlx5_ifc_teardown_hca_in_bits { 3454 u8 opcode[0x10]; 3455 u8 reserved_0[0x10]; 3456 3457 u8 reserved_1[0x10]; 3458 u8 op_mod[0x10]; 3459 3460 u8 reserved_2[0x10]; 3461 u8 profile[0x10]; 3462 3463 u8 reserved_3[0x20]; 3464 }; 3465 3466 struct mlx5_ifc_set_delay_drop_params_out_bits { 3467 u8 status[0x8]; 3468 u8 reserved_at_8[0x18]; 3469 3470 u8 syndrome[0x20]; 3471 3472 u8 reserved_at_40[0x40]; 3473 }; 3474 3475 struct mlx5_ifc_set_delay_drop_params_in_bits { 3476 u8 opcode[0x10]; 3477 u8 reserved_at_10[0x10]; 3478 3479 u8 reserved_at_20[0x10]; 3480 u8 op_mod[0x10]; 3481 3482 u8 reserved_at_40[0x20]; 3483 3484 u8 reserved_at_60[0x10]; 3485 u8 delay_drop_timeout[0x10]; 3486 }; 3487 3488 struct mlx5_ifc_query_delay_drop_params_out_bits { 3489 u8 status[0x8]; 3490 u8 reserved_at_8[0x18]; 3491 3492 u8 syndrome[0x20]; 3493 3494 u8 reserved_at_40[0x20]; 3495 3496 u8 reserved_at_60[0x10]; 3497 u8 delay_drop_timeout[0x10]; 3498 }; 3499 3500 struct mlx5_ifc_query_delay_drop_params_in_bits { 3501 u8 opcode[0x10]; 3502 u8 reserved_at_10[0x10]; 3503 3504 u8 reserved_at_20[0x10]; 3505 u8 op_mod[0x10]; 3506 3507 u8 reserved_at_40[0x40]; 3508 }; 3509 3510 struct mlx5_ifc_suspend_qp_out_bits { 3511 u8 status[0x8]; 3512 u8 reserved_0[0x18]; 3513 3514 u8 syndrome[0x20]; 3515 3516 u8 reserved_1[0x40]; 3517 }; 3518 3519 struct mlx5_ifc_suspend_qp_in_bits { 3520 u8 opcode[0x10]; 3521 u8 reserved_0[0x10]; 3522 3523 u8 reserved_1[0x10]; 3524 u8 op_mod[0x10]; 3525 3526 u8 reserved_2[0x8]; 3527 u8 qpn[0x18]; 3528 3529 u8 reserved_3[0x20]; 3530 }; 3531 3532 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3533 u8 status[0x8]; 3534 u8 reserved_0[0x18]; 3535 3536 u8 syndrome[0x20]; 3537 3538 u8 reserved_1[0x40]; 3539 }; 3540 3541 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3542 u8 opcode[0x10]; 3543 u8 uid[0x10]; 3544 3545 u8 reserved_1[0x10]; 3546 u8 op_mod[0x10]; 3547 3548 u8 reserved_2[0x8]; 3549 u8 qpn[0x18]; 3550 3551 u8 reserved_3[0x20]; 3552 3553 u8 opt_param_mask[0x20]; 3554 3555 u8 reserved_4[0x20]; 3556 3557 struct mlx5_ifc_qpc_bits qpc; 3558 3559 u8 reserved_5[0x80]; 3560 }; 3561 3562 struct mlx5_ifc_sqd2rts_qp_out_bits { 3563 u8 status[0x8]; 3564 u8 reserved_0[0x18]; 3565 3566 u8 syndrome[0x20]; 3567 3568 u8 reserved_1[0x40]; 3569 }; 3570 3571 struct mlx5_ifc_sqd2rts_qp_in_bits { 3572 u8 opcode[0x10]; 3573 u8 reserved_0[0x10]; 3574 3575 u8 reserved_1[0x10]; 3576 u8 op_mod[0x10]; 3577 3578 u8 reserved_2[0x8]; 3579 u8 qpn[0x18]; 3580 3581 u8 reserved_3[0x20]; 3582 3583 u8 opt_param_mask[0x20]; 3584 3585 u8 reserved_4[0x20]; 3586 3587 struct mlx5_ifc_qpc_bits qpc; 3588 3589 u8 reserved_5[0x80]; 3590 }; 3591 3592 struct mlx5_ifc_set_wol_rol_out_bits { 3593 u8 status[0x8]; 3594 u8 reserved_0[0x18]; 3595 3596 u8 syndrome[0x20]; 3597 3598 u8 reserved_1[0x40]; 3599 }; 3600 3601 struct mlx5_ifc_set_wol_rol_in_bits { 3602 u8 opcode[0x10]; 3603 u8 reserved_0[0x10]; 3604 3605 u8 reserved_1[0x10]; 3606 u8 op_mod[0x10]; 3607 3608 u8 rol_mode_valid[0x1]; 3609 u8 wol_mode_valid[0x1]; 3610 u8 reserved_2[0xe]; 3611 u8 rol_mode[0x8]; 3612 u8 wol_mode[0x8]; 3613 3614 u8 reserved_3[0x20]; 3615 }; 3616 3617 struct mlx5_ifc_set_roce_address_out_bits { 3618 u8 status[0x8]; 3619 u8 reserved_0[0x18]; 3620 3621 u8 syndrome[0x20]; 3622 3623 u8 reserved_1[0x40]; 3624 }; 3625 3626 struct mlx5_ifc_set_roce_address_in_bits { 3627 u8 opcode[0x10]; 3628 u8 reserved_0[0x10]; 3629 3630 u8 reserved_1[0x10]; 3631 u8 op_mod[0x10]; 3632 3633 u8 roce_address_index[0x10]; 3634 u8 reserved_2[0x10]; 3635 3636 u8 reserved_3[0x20]; 3637 3638 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3639 }; 3640 3641 struct mlx5_ifc_set_rdb_out_bits { 3642 u8 status[0x8]; 3643 u8 reserved_0[0x18]; 3644 3645 u8 syndrome[0x20]; 3646 3647 u8 reserved_1[0x40]; 3648 }; 3649 3650 struct mlx5_ifc_set_rdb_in_bits { 3651 u8 opcode[0x10]; 3652 u8 reserved_0[0x10]; 3653 3654 u8 reserved_1[0x10]; 3655 u8 op_mod[0x10]; 3656 3657 u8 reserved_2[0x8]; 3658 u8 qpn[0x18]; 3659 3660 u8 reserved_3[0x18]; 3661 u8 rdb_list_size[0x8]; 3662 3663 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3664 }; 3665 3666 struct mlx5_ifc_set_mad_demux_out_bits { 3667 u8 status[0x8]; 3668 u8 reserved_0[0x18]; 3669 3670 u8 syndrome[0x20]; 3671 3672 u8 reserved_1[0x40]; 3673 }; 3674 3675 enum { 3676 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3677 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3678 }; 3679 3680 struct mlx5_ifc_set_mad_demux_in_bits { 3681 u8 opcode[0x10]; 3682 u8 reserved_0[0x10]; 3683 3684 u8 reserved_1[0x10]; 3685 u8 op_mod[0x10]; 3686 3687 u8 reserved_2[0x20]; 3688 3689 u8 reserved_3[0x6]; 3690 u8 demux_mode[0x2]; 3691 u8 reserved_4[0x18]; 3692 }; 3693 3694 struct mlx5_ifc_set_l2_table_entry_out_bits { 3695 u8 status[0x8]; 3696 u8 reserved_0[0x18]; 3697 3698 u8 syndrome[0x20]; 3699 3700 u8 reserved_1[0x40]; 3701 }; 3702 3703 struct mlx5_ifc_set_l2_table_entry_in_bits { 3704 u8 opcode[0x10]; 3705 u8 reserved_0[0x10]; 3706 3707 u8 reserved_1[0x10]; 3708 u8 op_mod[0x10]; 3709 3710 u8 reserved_2[0x60]; 3711 3712 u8 reserved_3[0x8]; 3713 u8 table_index[0x18]; 3714 3715 u8 reserved_4[0x20]; 3716 3717 u8 reserved_5[0x13]; 3718 u8 vlan_valid[0x1]; 3719 u8 vlan[0xc]; 3720 3721 struct mlx5_ifc_mac_address_layout_bits mac_address; 3722 3723 u8 reserved_6[0xc0]; 3724 }; 3725 3726 struct mlx5_ifc_set_issi_out_bits { 3727 u8 status[0x8]; 3728 u8 reserved_0[0x18]; 3729 3730 u8 syndrome[0x20]; 3731 3732 u8 reserved_1[0x40]; 3733 }; 3734 3735 struct mlx5_ifc_set_issi_in_bits { 3736 u8 opcode[0x10]; 3737 u8 reserved_0[0x10]; 3738 3739 u8 reserved_1[0x10]; 3740 u8 op_mod[0x10]; 3741 3742 u8 reserved_2[0x10]; 3743 u8 current_issi[0x10]; 3744 3745 u8 reserved_3[0x20]; 3746 }; 3747 3748 struct mlx5_ifc_set_hca_cap_out_bits { 3749 u8 status[0x8]; 3750 u8 reserved_0[0x18]; 3751 3752 u8 syndrome[0x20]; 3753 3754 u8 reserved_1[0x40]; 3755 }; 3756 3757 struct mlx5_ifc_set_hca_cap_in_bits { 3758 u8 opcode[0x10]; 3759 u8 reserved_0[0x10]; 3760 3761 u8 reserved_1[0x10]; 3762 u8 op_mod[0x10]; 3763 3764 u8 reserved_2[0x40]; 3765 3766 union mlx5_ifc_hca_cap_union_bits capability; 3767 }; 3768 3769 enum { 3770 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3771 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3772 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3773 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3774 }; 3775 3776 struct mlx5_ifc_set_flow_table_root_out_bits { 3777 u8 status[0x8]; 3778 u8 reserved_0[0x18]; 3779 3780 u8 syndrome[0x20]; 3781 3782 u8 reserved_1[0x40]; 3783 }; 3784 3785 struct mlx5_ifc_set_flow_table_root_in_bits { 3786 u8 opcode[0x10]; 3787 u8 reserved_0[0x10]; 3788 3789 u8 reserved_1[0x10]; 3790 u8 op_mod[0x10]; 3791 3792 u8 other_vport[0x1]; 3793 u8 reserved_2[0xf]; 3794 u8 vport_number[0x10]; 3795 3796 u8 reserved_3[0x20]; 3797 3798 u8 table_type[0x8]; 3799 u8 reserved_4[0x18]; 3800 3801 u8 reserved_5[0x8]; 3802 u8 table_id[0x18]; 3803 3804 u8 reserved_6[0x8]; 3805 u8 underlay_qpn[0x18]; 3806 3807 u8 reserved_7[0x120]; 3808 }; 3809 3810 struct mlx5_ifc_set_fte_out_bits { 3811 u8 status[0x8]; 3812 u8 reserved_0[0x18]; 3813 3814 u8 syndrome[0x20]; 3815 3816 u8 reserved_1[0x40]; 3817 }; 3818 3819 struct mlx5_ifc_set_fte_in_bits { 3820 u8 opcode[0x10]; 3821 u8 reserved_0[0x10]; 3822 3823 u8 reserved_1[0x10]; 3824 u8 op_mod[0x10]; 3825 3826 u8 other_vport[0x1]; 3827 u8 reserved_2[0xf]; 3828 u8 vport_number[0x10]; 3829 3830 u8 reserved_3[0x20]; 3831 3832 u8 table_type[0x8]; 3833 u8 reserved_4[0x18]; 3834 3835 u8 reserved_5[0x8]; 3836 u8 table_id[0x18]; 3837 3838 u8 reserved_6[0x18]; 3839 u8 modify_enable_mask[0x8]; 3840 3841 u8 reserved_7[0x20]; 3842 3843 u8 flow_index[0x20]; 3844 3845 u8 reserved_8[0xe0]; 3846 3847 struct mlx5_ifc_flow_context_bits flow_context; 3848 }; 3849 3850 struct mlx5_ifc_set_driver_version_out_bits { 3851 u8 status[0x8]; 3852 u8 reserved_0[0x18]; 3853 3854 u8 syndrome[0x20]; 3855 3856 u8 reserved_1[0x40]; 3857 }; 3858 3859 struct mlx5_ifc_set_driver_version_in_bits { 3860 u8 opcode[0x10]; 3861 u8 reserved_0[0x10]; 3862 3863 u8 reserved_1[0x10]; 3864 u8 op_mod[0x10]; 3865 3866 u8 reserved_2[0x40]; 3867 3868 u8 driver_version[64][0x8]; 3869 }; 3870 3871 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3872 u8 status[0x8]; 3873 u8 reserved_0[0x18]; 3874 3875 u8 syndrome[0x20]; 3876 3877 u8 reserved_1[0x40]; 3878 }; 3879 3880 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3881 u8 opcode[0x10]; 3882 u8 reserved_0[0x10]; 3883 3884 u8 reserved_1[0x10]; 3885 u8 op_mod[0x10]; 3886 3887 u8 enable[0x1]; 3888 u8 reserved_2[0x1f]; 3889 3890 u8 reserved_3[0x160]; 3891 3892 struct mlx5_ifc_cmd_pas_bits pas; 3893 }; 3894 3895 struct mlx5_ifc_set_burst_size_out_bits { 3896 u8 status[0x8]; 3897 u8 reserved_0[0x18]; 3898 3899 u8 syndrome[0x20]; 3900 3901 u8 reserved_1[0x40]; 3902 }; 3903 3904 struct mlx5_ifc_set_burst_size_in_bits { 3905 u8 opcode[0x10]; 3906 u8 reserved_0[0x10]; 3907 3908 u8 reserved_1[0x10]; 3909 u8 op_mod[0x10]; 3910 3911 u8 reserved_2[0x20]; 3912 3913 u8 reserved_3[0x9]; 3914 u8 device_burst_size[0x17]; 3915 }; 3916 3917 struct mlx5_ifc_rts2rts_qp_out_bits { 3918 u8 status[0x8]; 3919 u8 reserved_0[0x18]; 3920 3921 u8 syndrome[0x20]; 3922 3923 u8 reserved_1[0x40]; 3924 }; 3925 3926 struct mlx5_ifc_rts2rts_qp_in_bits { 3927 u8 opcode[0x10]; 3928 u8 uid[0x10]; 3929 3930 u8 reserved_1[0x10]; 3931 u8 op_mod[0x10]; 3932 3933 u8 reserved_2[0x8]; 3934 u8 qpn[0x18]; 3935 3936 u8 reserved_3[0x20]; 3937 3938 u8 opt_param_mask[0x20]; 3939 3940 u8 reserved_4[0x20]; 3941 3942 struct mlx5_ifc_qpc_bits qpc; 3943 3944 u8 reserved_5[0x80]; 3945 }; 3946 3947 struct mlx5_ifc_rtr2rts_qp_out_bits { 3948 u8 status[0x8]; 3949 u8 reserved_0[0x18]; 3950 3951 u8 syndrome[0x20]; 3952 3953 u8 reserved_1[0x40]; 3954 }; 3955 3956 struct mlx5_ifc_rtr2rts_qp_in_bits { 3957 u8 opcode[0x10]; 3958 u8 uid[0x10]; 3959 3960 u8 reserved_1[0x10]; 3961 u8 op_mod[0x10]; 3962 3963 u8 reserved_2[0x8]; 3964 u8 qpn[0x18]; 3965 3966 u8 reserved_3[0x20]; 3967 3968 u8 opt_param_mask[0x20]; 3969 3970 u8 reserved_4[0x20]; 3971 3972 struct mlx5_ifc_qpc_bits qpc; 3973 3974 u8 reserved_5[0x80]; 3975 }; 3976 3977 struct mlx5_ifc_rst2init_qp_out_bits { 3978 u8 status[0x8]; 3979 u8 reserved_0[0x18]; 3980 3981 u8 syndrome[0x20]; 3982 3983 u8 reserved_1[0x40]; 3984 }; 3985 3986 struct mlx5_ifc_rst2init_qp_in_bits { 3987 u8 opcode[0x10]; 3988 u8 uid[0x10]; 3989 3990 u8 reserved_1[0x10]; 3991 u8 op_mod[0x10]; 3992 3993 u8 reserved_2[0x8]; 3994 u8 qpn[0x18]; 3995 3996 u8 reserved_3[0x20]; 3997 3998 u8 opt_param_mask[0x20]; 3999 4000 u8 reserved_4[0x20]; 4001 4002 struct mlx5_ifc_qpc_bits qpc; 4003 4004 u8 reserved_5[0x80]; 4005 }; 4006 4007 struct mlx5_ifc_resume_qp_out_bits { 4008 u8 status[0x8]; 4009 u8 reserved_0[0x18]; 4010 4011 u8 syndrome[0x20]; 4012 4013 u8 reserved_1[0x40]; 4014 }; 4015 4016 struct mlx5_ifc_resume_qp_in_bits { 4017 u8 opcode[0x10]; 4018 u8 reserved_0[0x10]; 4019 4020 u8 reserved_1[0x10]; 4021 u8 op_mod[0x10]; 4022 4023 u8 reserved_2[0x8]; 4024 u8 qpn[0x18]; 4025 4026 u8 reserved_3[0x20]; 4027 }; 4028 4029 struct mlx5_ifc_query_xrc_srq_out_bits { 4030 u8 status[0x8]; 4031 u8 reserved_0[0x18]; 4032 4033 u8 syndrome[0x20]; 4034 4035 u8 reserved_1[0x40]; 4036 4037 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4038 4039 u8 reserved_2[0x600]; 4040 4041 u8 pas[0][0x40]; 4042 }; 4043 4044 struct mlx5_ifc_query_xrc_srq_in_bits { 4045 u8 opcode[0x10]; 4046 u8 reserved_0[0x10]; 4047 4048 u8 reserved_1[0x10]; 4049 u8 op_mod[0x10]; 4050 4051 u8 reserved_2[0x8]; 4052 u8 xrc_srqn[0x18]; 4053 4054 u8 reserved_3[0x20]; 4055 }; 4056 4057 struct mlx5_ifc_query_wol_rol_out_bits { 4058 u8 status[0x8]; 4059 u8 reserved_0[0x18]; 4060 4061 u8 syndrome[0x20]; 4062 4063 u8 reserved_1[0x10]; 4064 u8 rol_mode[0x8]; 4065 u8 wol_mode[0x8]; 4066 4067 u8 reserved_2[0x20]; 4068 }; 4069 4070 struct mlx5_ifc_query_wol_rol_in_bits { 4071 u8 opcode[0x10]; 4072 u8 reserved_0[0x10]; 4073 4074 u8 reserved_1[0x10]; 4075 u8 op_mod[0x10]; 4076 4077 u8 reserved_2[0x40]; 4078 }; 4079 4080 enum { 4081 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4082 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4083 }; 4084 4085 struct mlx5_ifc_query_vport_state_out_bits { 4086 u8 status[0x8]; 4087 u8 reserved_0[0x18]; 4088 4089 u8 syndrome[0x20]; 4090 4091 u8 reserved_1[0x20]; 4092 4093 u8 reserved_2[0x18]; 4094 u8 admin_state[0x4]; 4095 u8 state[0x4]; 4096 }; 4097 4098 enum { 4099 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4100 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4101 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4102 }; 4103 4104 struct mlx5_ifc_query_vport_state_in_bits { 4105 u8 opcode[0x10]; 4106 u8 reserved_0[0x10]; 4107 4108 u8 reserved_1[0x10]; 4109 u8 op_mod[0x10]; 4110 4111 u8 other_vport[0x1]; 4112 u8 reserved_2[0xf]; 4113 u8 vport_number[0x10]; 4114 4115 u8 reserved_3[0x20]; 4116 }; 4117 4118 struct mlx5_ifc_query_vnic_env_out_bits { 4119 u8 status[0x8]; 4120 u8 reserved_at_8[0x18]; 4121 4122 u8 syndrome[0x20]; 4123 4124 u8 reserved_at_40[0x40]; 4125 4126 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4127 }; 4128 4129 enum { 4130 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4131 }; 4132 4133 struct mlx5_ifc_query_vnic_env_in_bits { 4134 u8 opcode[0x10]; 4135 u8 reserved_at_10[0x10]; 4136 4137 u8 reserved_at_20[0x10]; 4138 u8 op_mod[0x10]; 4139 4140 u8 other_vport[0x1]; 4141 u8 reserved_at_41[0xf]; 4142 u8 vport_number[0x10]; 4143 4144 u8 reserved_at_60[0x20]; 4145 }; 4146 4147 struct mlx5_ifc_query_vport_counter_out_bits { 4148 u8 status[0x8]; 4149 u8 reserved_0[0x18]; 4150 4151 u8 syndrome[0x20]; 4152 4153 u8 reserved_1[0x40]; 4154 4155 struct mlx5_ifc_traffic_counter_bits received_errors; 4156 4157 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4158 4159 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4160 4161 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4162 4163 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4164 4165 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4166 4167 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4168 4169 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4170 4171 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4172 4173 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4174 4175 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4176 4177 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4178 4179 u8 reserved_2[0xa00]; 4180 }; 4181 4182 enum { 4183 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4184 }; 4185 4186 struct mlx5_ifc_query_vport_counter_in_bits { 4187 u8 opcode[0x10]; 4188 u8 reserved_0[0x10]; 4189 4190 u8 reserved_1[0x10]; 4191 u8 op_mod[0x10]; 4192 4193 u8 other_vport[0x1]; 4194 u8 reserved_2[0xb]; 4195 u8 port_num[0x4]; 4196 u8 vport_number[0x10]; 4197 4198 u8 reserved_3[0x60]; 4199 4200 u8 clear[0x1]; 4201 u8 reserved_4[0x1f]; 4202 4203 u8 reserved_5[0x20]; 4204 }; 4205 4206 struct mlx5_ifc_query_tis_out_bits { 4207 u8 status[0x8]; 4208 u8 reserved_0[0x18]; 4209 4210 u8 syndrome[0x20]; 4211 4212 u8 reserved_1[0x40]; 4213 4214 struct mlx5_ifc_tisc_bits tis_context; 4215 }; 4216 4217 struct mlx5_ifc_query_tis_in_bits { 4218 u8 opcode[0x10]; 4219 u8 reserved_0[0x10]; 4220 4221 u8 reserved_1[0x10]; 4222 u8 op_mod[0x10]; 4223 4224 u8 reserved_2[0x8]; 4225 u8 tisn[0x18]; 4226 4227 u8 reserved_3[0x20]; 4228 }; 4229 4230 struct mlx5_ifc_query_tir_out_bits { 4231 u8 status[0x8]; 4232 u8 reserved_0[0x18]; 4233 4234 u8 syndrome[0x20]; 4235 4236 u8 reserved_1[0xc0]; 4237 4238 struct mlx5_ifc_tirc_bits tir_context; 4239 }; 4240 4241 struct mlx5_ifc_query_tir_in_bits { 4242 u8 opcode[0x10]; 4243 u8 reserved_0[0x10]; 4244 4245 u8 reserved_1[0x10]; 4246 u8 op_mod[0x10]; 4247 4248 u8 reserved_2[0x8]; 4249 u8 tirn[0x18]; 4250 4251 u8 reserved_3[0x20]; 4252 }; 4253 4254 struct mlx5_ifc_query_srq_out_bits { 4255 u8 status[0x8]; 4256 u8 reserved_0[0x18]; 4257 4258 u8 syndrome[0x20]; 4259 4260 u8 reserved_1[0x40]; 4261 4262 struct mlx5_ifc_srqc_bits srq_context_entry; 4263 4264 u8 reserved_2[0x600]; 4265 4266 u8 pas[0][0x40]; 4267 }; 4268 4269 struct mlx5_ifc_query_srq_in_bits { 4270 u8 opcode[0x10]; 4271 u8 reserved_0[0x10]; 4272 4273 u8 reserved_1[0x10]; 4274 u8 op_mod[0x10]; 4275 4276 u8 reserved_2[0x8]; 4277 u8 srqn[0x18]; 4278 4279 u8 reserved_3[0x20]; 4280 }; 4281 4282 struct mlx5_ifc_query_sq_out_bits { 4283 u8 status[0x8]; 4284 u8 reserved_0[0x18]; 4285 4286 u8 syndrome[0x20]; 4287 4288 u8 reserved_1[0xc0]; 4289 4290 struct mlx5_ifc_sqc_bits sq_context; 4291 }; 4292 4293 struct mlx5_ifc_query_sq_in_bits { 4294 u8 opcode[0x10]; 4295 u8 reserved_0[0x10]; 4296 4297 u8 reserved_1[0x10]; 4298 u8 op_mod[0x10]; 4299 4300 u8 reserved_2[0x8]; 4301 u8 sqn[0x18]; 4302 4303 u8 reserved_3[0x20]; 4304 }; 4305 4306 struct mlx5_ifc_query_special_contexts_out_bits { 4307 u8 status[0x8]; 4308 u8 reserved_0[0x18]; 4309 4310 u8 syndrome[0x20]; 4311 4312 u8 dump_fill_mkey[0x20]; 4313 4314 u8 resd_lkey[0x20]; 4315 }; 4316 4317 struct mlx5_ifc_query_special_contexts_in_bits { 4318 u8 opcode[0x10]; 4319 u8 reserved_0[0x10]; 4320 4321 u8 reserved_1[0x10]; 4322 u8 op_mod[0x10]; 4323 4324 u8 reserved_2[0x40]; 4325 }; 4326 4327 struct mlx5_ifc_query_scheduling_element_out_bits { 4328 u8 status[0x8]; 4329 u8 reserved_at_8[0x18]; 4330 4331 u8 syndrome[0x20]; 4332 4333 u8 reserved_at_40[0xc0]; 4334 4335 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4336 4337 u8 reserved_at_300[0x100]; 4338 }; 4339 4340 enum { 4341 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4342 }; 4343 4344 struct mlx5_ifc_query_scheduling_element_in_bits { 4345 u8 opcode[0x10]; 4346 u8 reserved_at_10[0x10]; 4347 4348 u8 reserved_at_20[0x10]; 4349 u8 op_mod[0x10]; 4350 4351 u8 scheduling_hierarchy[0x8]; 4352 u8 reserved_at_48[0x18]; 4353 4354 u8 scheduling_element_id[0x20]; 4355 4356 u8 reserved_at_80[0x180]; 4357 }; 4358 4359 struct mlx5_ifc_query_rqt_out_bits { 4360 u8 status[0x8]; 4361 u8 reserved_0[0x18]; 4362 4363 u8 syndrome[0x20]; 4364 4365 u8 reserved_1[0xc0]; 4366 4367 struct mlx5_ifc_rqtc_bits rqt_context; 4368 }; 4369 4370 struct mlx5_ifc_query_rqt_in_bits { 4371 u8 opcode[0x10]; 4372 u8 reserved_0[0x10]; 4373 4374 u8 reserved_1[0x10]; 4375 u8 op_mod[0x10]; 4376 4377 u8 reserved_2[0x8]; 4378 u8 rqtn[0x18]; 4379 4380 u8 reserved_3[0x20]; 4381 }; 4382 4383 struct mlx5_ifc_query_rq_out_bits { 4384 u8 status[0x8]; 4385 u8 reserved_0[0x18]; 4386 4387 u8 syndrome[0x20]; 4388 4389 u8 reserved_1[0xc0]; 4390 4391 struct mlx5_ifc_rqc_bits rq_context; 4392 }; 4393 4394 struct mlx5_ifc_query_rq_in_bits { 4395 u8 opcode[0x10]; 4396 u8 reserved_0[0x10]; 4397 4398 u8 reserved_1[0x10]; 4399 u8 op_mod[0x10]; 4400 4401 u8 reserved_2[0x8]; 4402 u8 rqn[0x18]; 4403 4404 u8 reserved_3[0x20]; 4405 }; 4406 4407 struct mlx5_ifc_query_roce_address_out_bits { 4408 u8 status[0x8]; 4409 u8 reserved_0[0x18]; 4410 4411 u8 syndrome[0x20]; 4412 4413 u8 reserved_1[0x40]; 4414 4415 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4416 }; 4417 4418 struct mlx5_ifc_query_roce_address_in_bits { 4419 u8 opcode[0x10]; 4420 u8 reserved_0[0x10]; 4421 4422 u8 reserved_1[0x10]; 4423 u8 op_mod[0x10]; 4424 4425 u8 roce_address_index[0x10]; 4426 u8 reserved_2[0x10]; 4427 4428 u8 reserved_3[0x20]; 4429 }; 4430 4431 struct mlx5_ifc_query_rmp_out_bits { 4432 u8 status[0x8]; 4433 u8 reserved_0[0x18]; 4434 4435 u8 syndrome[0x20]; 4436 4437 u8 reserved_1[0xc0]; 4438 4439 struct mlx5_ifc_rmpc_bits rmp_context; 4440 }; 4441 4442 struct mlx5_ifc_query_rmp_in_bits { 4443 u8 opcode[0x10]; 4444 u8 reserved_0[0x10]; 4445 4446 u8 reserved_1[0x10]; 4447 u8 op_mod[0x10]; 4448 4449 u8 reserved_2[0x8]; 4450 u8 rmpn[0x18]; 4451 4452 u8 reserved_3[0x20]; 4453 }; 4454 4455 struct mlx5_ifc_query_rdb_out_bits { 4456 u8 status[0x8]; 4457 u8 reserved_0[0x18]; 4458 4459 u8 syndrome[0x20]; 4460 4461 u8 reserved_1[0x20]; 4462 4463 u8 reserved_2[0x18]; 4464 u8 rdb_list_size[0x8]; 4465 4466 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4467 }; 4468 4469 struct mlx5_ifc_query_rdb_in_bits { 4470 u8 opcode[0x10]; 4471 u8 reserved_0[0x10]; 4472 4473 u8 reserved_1[0x10]; 4474 u8 op_mod[0x10]; 4475 4476 u8 reserved_2[0x8]; 4477 u8 qpn[0x18]; 4478 4479 u8 reserved_3[0x20]; 4480 }; 4481 4482 struct mlx5_ifc_query_qp_out_bits { 4483 u8 status[0x8]; 4484 u8 reserved_0[0x18]; 4485 4486 u8 syndrome[0x20]; 4487 4488 u8 reserved_1[0x40]; 4489 4490 u8 opt_param_mask[0x20]; 4491 4492 u8 reserved_2[0x20]; 4493 4494 struct mlx5_ifc_qpc_bits qpc; 4495 4496 u8 reserved_3[0x80]; 4497 4498 u8 pas[0][0x40]; 4499 }; 4500 4501 struct mlx5_ifc_query_qp_in_bits { 4502 u8 opcode[0x10]; 4503 u8 reserved_0[0x10]; 4504 4505 u8 reserved_1[0x10]; 4506 u8 op_mod[0x10]; 4507 4508 u8 reserved_2[0x8]; 4509 u8 qpn[0x18]; 4510 4511 u8 reserved_3[0x20]; 4512 }; 4513 4514 struct mlx5_ifc_query_q_counter_out_bits { 4515 u8 status[0x8]; 4516 u8 reserved_0[0x18]; 4517 4518 u8 syndrome[0x20]; 4519 4520 u8 reserved_1[0x40]; 4521 4522 u8 rx_write_requests[0x20]; 4523 4524 u8 reserved_2[0x20]; 4525 4526 u8 rx_read_requests[0x20]; 4527 4528 u8 reserved_3[0x20]; 4529 4530 u8 rx_atomic_requests[0x20]; 4531 4532 u8 reserved_4[0x20]; 4533 4534 u8 rx_dct_connect[0x20]; 4535 4536 u8 reserved_5[0x20]; 4537 4538 u8 out_of_buffer[0x20]; 4539 4540 u8 reserved_7[0x20]; 4541 4542 u8 out_of_sequence[0x20]; 4543 4544 u8 reserved_8[0x20]; 4545 4546 u8 duplicate_request[0x20]; 4547 4548 u8 reserved_9[0x20]; 4549 4550 u8 rnr_nak_retry_err[0x20]; 4551 4552 u8 reserved_10[0x20]; 4553 4554 u8 packet_seq_err[0x20]; 4555 4556 u8 reserved_11[0x20]; 4557 4558 u8 implied_nak_seq_err[0x20]; 4559 4560 u8 reserved_12[0x20]; 4561 4562 u8 local_ack_timeout_err[0x20]; 4563 4564 u8 reserved_13[0x20]; 4565 4566 u8 resp_rnr_nak[0x20]; 4567 4568 u8 reserved_14[0x20]; 4569 4570 u8 req_rnr_retries_exceeded[0x20]; 4571 4572 u8 reserved_15[0x460]; 4573 }; 4574 4575 struct mlx5_ifc_query_q_counter_in_bits { 4576 u8 opcode[0x10]; 4577 u8 reserved_0[0x10]; 4578 4579 u8 reserved_1[0x10]; 4580 u8 op_mod[0x10]; 4581 4582 u8 reserved_2[0x80]; 4583 4584 u8 clear[0x1]; 4585 u8 reserved_3[0x1f]; 4586 4587 u8 reserved_4[0x18]; 4588 u8 counter_set_id[0x8]; 4589 }; 4590 4591 struct mlx5_ifc_query_pages_out_bits { 4592 u8 status[0x8]; 4593 u8 reserved_0[0x18]; 4594 4595 u8 syndrome[0x20]; 4596 4597 u8 reserved_1[0x10]; 4598 u8 function_id[0x10]; 4599 4600 u8 num_pages[0x20]; 4601 }; 4602 4603 enum { 4604 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4605 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4606 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4607 }; 4608 4609 struct mlx5_ifc_query_pages_in_bits { 4610 u8 opcode[0x10]; 4611 u8 reserved_0[0x10]; 4612 4613 u8 reserved_1[0x10]; 4614 u8 op_mod[0x10]; 4615 4616 u8 reserved_2[0x10]; 4617 u8 function_id[0x10]; 4618 4619 u8 reserved_3[0x20]; 4620 }; 4621 4622 struct mlx5_ifc_query_nic_vport_context_out_bits { 4623 u8 status[0x8]; 4624 u8 reserved_0[0x18]; 4625 4626 u8 syndrome[0x20]; 4627 4628 u8 reserved_1[0x40]; 4629 4630 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4631 }; 4632 4633 struct mlx5_ifc_query_nic_vport_context_in_bits { 4634 u8 opcode[0x10]; 4635 u8 reserved_0[0x10]; 4636 4637 u8 reserved_1[0x10]; 4638 u8 op_mod[0x10]; 4639 4640 u8 other_vport[0x1]; 4641 u8 reserved_2[0xf]; 4642 u8 vport_number[0x10]; 4643 4644 u8 reserved_3[0x5]; 4645 u8 allowed_list_type[0x3]; 4646 u8 reserved_4[0x18]; 4647 }; 4648 4649 struct mlx5_ifc_query_mkey_out_bits { 4650 u8 status[0x8]; 4651 u8 reserved_0[0x18]; 4652 4653 u8 syndrome[0x20]; 4654 4655 u8 reserved_1[0x40]; 4656 4657 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4658 4659 u8 reserved_2[0x600]; 4660 4661 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4662 4663 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4664 }; 4665 4666 struct mlx5_ifc_query_mkey_in_bits { 4667 u8 opcode[0x10]; 4668 u8 reserved_0[0x10]; 4669 4670 u8 reserved_1[0x10]; 4671 u8 op_mod[0x10]; 4672 4673 u8 reserved_2[0x8]; 4674 u8 mkey_index[0x18]; 4675 4676 u8 pg_access[0x1]; 4677 u8 reserved_3[0x1f]; 4678 }; 4679 4680 struct mlx5_ifc_query_mad_demux_out_bits { 4681 u8 status[0x8]; 4682 u8 reserved_0[0x18]; 4683 4684 u8 syndrome[0x20]; 4685 4686 u8 reserved_1[0x40]; 4687 4688 u8 mad_dumux_parameters_block[0x20]; 4689 }; 4690 4691 struct mlx5_ifc_query_mad_demux_in_bits { 4692 u8 opcode[0x10]; 4693 u8 reserved_0[0x10]; 4694 4695 u8 reserved_1[0x10]; 4696 u8 op_mod[0x10]; 4697 4698 u8 reserved_2[0x40]; 4699 }; 4700 4701 struct mlx5_ifc_query_l2_table_entry_out_bits { 4702 u8 status[0x8]; 4703 u8 reserved_0[0x18]; 4704 4705 u8 syndrome[0x20]; 4706 4707 u8 reserved_1[0xa0]; 4708 4709 u8 reserved_2[0x13]; 4710 u8 vlan_valid[0x1]; 4711 u8 vlan[0xc]; 4712 4713 struct mlx5_ifc_mac_address_layout_bits mac_address; 4714 4715 u8 reserved_3[0xc0]; 4716 }; 4717 4718 struct mlx5_ifc_query_l2_table_entry_in_bits { 4719 u8 opcode[0x10]; 4720 u8 reserved_0[0x10]; 4721 4722 u8 reserved_1[0x10]; 4723 u8 op_mod[0x10]; 4724 4725 u8 reserved_2[0x60]; 4726 4727 u8 reserved_3[0x8]; 4728 u8 table_index[0x18]; 4729 4730 u8 reserved_4[0x140]; 4731 }; 4732 4733 struct mlx5_ifc_query_issi_out_bits { 4734 u8 status[0x8]; 4735 u8 reserved_0[0x18]; 4736 4737 u8 syndrome[0x20]; 4738 4739 u8 reserved_1[0x10]; 4740 u8 current_issi[0x10]; 4741 4742 u8 reserved_2[0xa0]; 4743 4744 u8 supported_issi_reserved[76][0x8]; 4745 u8 supported_issi_dw0[0x20]; 4746 }; 4747 4748 struct mlx5_ifc_query_issi_in_bits { 4749 u8 opcode[0x10]; 4750 u8 reserved_0[0x10]; 4751 4752 u8 reserved_1[0x10]; 4753 u8 op_mod[0x10]; 4754 4755 u8 reserved_2[0x40]; 4756 }; 4757 4758 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4759 u8 status[0x8]; 4760 u8 reserved_0[0x18]; 4761 4762 u8 syndrome[0x20]; 4763 4764 u8 reserved_1[0x40]; 4765 4766 struct mlx5_ifc_pkey_bits pkey[0]; 4767 }; 4768 4769 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4770 u8 opcode[0x10]; 4771 u8 reserved_0[0x10]; 4772 4773 u8 reserved_1[0x10]; 4774 u8 op_mod[0x10]; 4775 4776 u8 other_vport[0x1]; 4777 u8 reserved_2[0xb]; 4778 u8 port_num[0x4]; 4779 u8 vport_number[0x10]; 4780 4781 u8 reserved_3[0x10]; 4782 u8 pkey_index[0x10]; 4783 }; 4784 4785 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4786 u8 status[0x8]; 4787 u8 reserved_0[0x18]; 4788 4789 u8 syndrome[0x20]; 4790 4791 u8 reserved_1[0x20]; 4792 4793 u8 gids_num[0x10]; 4794 u8 reserved_2[0x10]; 4795 4796 struct mlx5_ifc_array128_auto_bits gid[0]; 4797 }; 4798 4799 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4800 u8 opcode[0x10]; 4801 u8 reserved_0[0x10]; 4802 4803 u8 reserved_1[0x10]; 4804 u8 op_mod[0x10]; 4805 4806 u8 other_vport[0x1]; 4807 u8 reserved_2[0xb]; 4808 u8 port_num[0x4]; 4809 u8 vport_number[0x10]; 4810 4811 u8 reserved_3[0x10]; 4812 u8 gid_index[0x10]; 4813 }; 4814 4815 struct mlx5_ifc_query_hca_vport_context_out_bits { 4816 u8 status[0x8]; 4817 u8 reserved_0[0x18]; 4818 4819 u8 syndrome[0x20]; 4820 4821 u8 reserved_1[0x40]; 4822 4823 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4824 }; 4825 4826 struct mlx5_ifc_query_hca_vport_context_in_bits { 4827 u8 opcode[0x10]; 4828 u8 reserved_0[0x10]; 4829 4830 u8 reserved_1[0x10]; 4831 u8 op_mod[0x10]; 4832 4833 u8 other_vport[0x1]; 4834 u8 reserved_2[0xb]; 4835 u8 port_num[0x4]; 4836 u8 vport_number[0x10]; 4837 4838 u8 reserved_3[0x20]; 4839 }; 4840 4841 struct mlx5_ifc_query_hca_cap_out_bits { 4842 u8 status[0x8]; 4843 u8 reserved_0[0x18]; 4844 4845 u8 syndrome[0x20]; 4846 4847 u8 reserved_1[0x40]; 4848 4849 union mlx5_ifc_hca_cap_union_bits capability; 4850 }; 4851 4852 struct mlx5_ifc_query_hca_cap_in_bits { 4853 u8 opcode[0x10]; 4854 u8 reserved_0[0x10]; 4855 4856 u8 reserved_1[0x10]; 4857 u8 op_mod[0x10]; 4858 4859 u8 reserved_2[0x40]; 4860 }; 4861 4862 struct mlx5_ifc_query_flow_table_out_bits { 4863 u8 status[0x8]; 4864 u8 reserved_at_8[0x18]; 4865 4866 u8 syndrome[0x20]; 4867 4868 u8 reserved_at_40[0x80]; 4869 4870 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4871 }; 4872 4873 struct mlx5_ifc_query_flow_table_in_bits { 4874 u8 opcode[0x10]; 4875 u8 reserved_0[0x10]; 4876 4877 u8 reserved_1[0x10]; 4878 u8 op_mod[0x10]; 4879 4880 u8 other_vport[0x1]; 4881 u8 reserved_2[0xf]; 4882 u8 vport_number[0x10]; 4883 4884 u8 reserved_3[0x20]; 4885 4886 u8 table_type[0x8]; 4887 u8 reserved_4[0x18]; 4888 4889 u8 reserved_5[0x8]; 4890 u8 table_id[0x18]; 4891 4892 u8 reserved_6[0x140]; 4893 }; 4894 4895 struct mlx5_ifc_query_fte_out_bits { 4896 u8 status[0x8]; 4897 u8 reserved_0[0x18]; 4898 4899 u8 syndrome[0x20]; 4900 4901 u8 reserved_1[0x1c0]; 4902 4903 struct mlx5_ifc_flow_context_bits flow_context; 4904 }; 4905 4906 struct mlx5_ifc_query_fte_in_bits { 4907 u8 opcode[0x10]; 4908 u8 reserved_0[0x10]; 4909 4910 u8 reserved_1[0x10]; 4911 u8 op_mod[0x10]; 4912 4913 u8 other_vport[0x1]; 4914 u8 reserved_2[0xf]; 4915 u8 vport_number[0x10]; 4916 4917 u8 reserved_3[0x20]; 4918 4919 u8 table_type[0x8]; 4920 u8 reserved_4[0x18]; 4921 4922 u8 reserved_5[0x8]; 4923 u8 table_id[0x18]; 4924 4925 u8 reserved_6[0x40]; 4926 4927 u8 flow_index[0x20]; 4928 4929 u8 reserved_7[0xe0]; 4930 }; 4931 4932 enum { 4933 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4934 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4935 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4936 }; 4937 4938 struct mlx5_ifc_query_flow_group_out_bits { 4939 u8 status[0x8]; 4940 u8 reserved_0[0x18]; 4941 4942 u8 syndrome[0x20]; 4943 4944 u8 reserved_1[0xa0]; 4945 4946 u8 start_flow_index[0x20]; 4947 4948 u8 reserved_2[0x20]; 4949 4950 u8 end_flow_index[0x20]; 4951 4952 u8 reserved_3[0xa0]; 4953 4954 u8 reserved_4[0x18]; 4955 u8 match_criteria_enable[0x8]; 4956 4957 struct mlx5_ifc_fte_match_param_bits match_criteria; 4958 4959 u8 reserved_5[0xe00]; 4960 }; 4961 4962 struct mlx5_ifc_query_flow_group_in_bits { 4963 u8 opcode[0x10]; 4964 u8 reserved_0[0x10]; 4965 4966 u8 reserved_1[0x10]; 4967 u8 op_mod[0x10]; 4968 4969 u8 other_vport[0x1]; 4970 u8 reserved_2[0xf]; 4971 u8 vport_number[0x10]; 4972 4973 u8 reserved_3[0x20]; 4974 4975 u8 table_type[0x8]; 4976 u8 reserved_4[0x18]; 4977 4978 u8 reserved_5[0x8]; 4979 u8 table_id[0x18]; 4980 4981 u8 group_id[0x20]; 4982 4983 u8 reserved_6[0x120]; 4984 }; 4985 4986 struct mlx5_ifc_query_flow_counter_out_bits { 4987 u8 status[0x8]; 4988 u8 reserved_at_8[0x18]; 4989 4990 u8 syndrome[0x20]; 4991 4992 u8 reserved_at_40[0x40]; 4993 4994 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4995 }; 4996 4997 struct mlx5_ifc_query_flow_counter_in_bits { 4998 u8 opcode[0x10]; 4999 u8 reserved_at_10[0x10]; 5000 5001 u8 reserved_at_20[0x10]; 5002 u8 op_mod[0x10]; 5003 5004 u8 reserved_at_40[0x80]; 5005 5006 u8 clear[0x1]; 5007 u8 reserved_at_c1[0xf]; 5008 u8 num_of_counters[0x10]; 5009 5010 u8 reserved_at_e0[0x10]; 5011 u8 flow_counter_id[0x10]; 5012 }; 5013 5014 struct mlx5_ifc_query_esw_vport_context_out_bits { 5015 u8 status[0x8]; 5016 u8 reserved_0[0x18]; 5017 5018 u8 syndrome[0x20]; 5019 5020 u8 reserved_1[0x40]; 5021 5022 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5023 }; 5024 5025 struct mlx5_ifc_query_esw_vport_context_in_bits { 5026 u8 opcode[0x10]; 5027 u8 reserved_0[0x10]; 5028 5029 u8 reserved_1[0x10]; 5030 u8 op_mod[0x10]; 5031 5032 u8 other_vport[0x1]; 5033 u8 reserved_2[0xf]; 5034 u8 vport_number[0x10]; 5035 5036 u8 reserved_3[0x20]; 5037 }; 5038 5039 struct mlx5_ifc_query_eq_out_bits { 5040 u8 status[0x8]; 5041 u8 reserved_0[0x18]; 5042 5043 u8 syndrome[0x20]; 5044 5045 u8 reserved_1[0x40]; 5046 5047 struct mlx5_ifc_eqc_bits eq_context_entry; 5048 5049 u8 reserved_2[0x40]; 5050 5051 u8 event_bitmask[0x40]; 5052 5053 u8 reserved_3[0x580]; 5054 5055 u8 pas[0][0x40]; 5056 }; 5057 5058 struct mlx5_ifc_query_eq_in_bits { 5059 u8 opcode[0x10]; 5060 u8 reserved_0[0x10]; 5061 5062 u8 reserved_1[0x10]; 5063 u8 op_mod[0x10]; 5064 5065 u8 reserved_2[0x18]; 5066 u8 eq_number[0x8]; 5067 5068 u8 reserved_3[0x20]; 5069 }; 5070 5071 struct mlx5_ifc_query_dct_out_bits { 5072 u8 status[0x8]; 5073 u8 reserved_0[0x18]; 5074 5075 u8 syndrome[0x20]; 5076 5077 u8 reserved_1[0x40]; 5078 5079 struct mlx5_ifc_dctc_bits dct_context_entry; 5080 5081 u8 reserved_2[0x180]; 5082 }; 5083 5084 struct mlx5_ifc_query_dct_in_bits { 5085 u8 opcode[0x10]; 5086 u8 reserved_0[0x10]; 5087 5088 u8 reserved_1[0x10]; 5089 u8 op_mod[0x10]; 5090 5091 u8 reserved_2[0x8]; 5092 u8 dctn[0x18]; 5093 5094 u8 reserved_3[0x20]; 5095 }; 5096 5097 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5098 u8 status[0x8]; 5099 u8 reserved_0[0x18]; 5100 5101 u8 syndrome[0x20]; 5102 5103 u8 enable[0x1]; 5104 u8 reserved_1[0x1f]; 5105 5106 u8 reserved_2[0x160]; 5107 5108 struct mlx5_ifc_cmd_pas_bits pas; 5109 }; 5110 5111 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_0[0x10]; 5114 5115 u8 reserved_1[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 reserved_2[0x40]; 5119 }; 5120 5121 struct mlx5_ifc_query_cq_out_bits { 5122 u8 status[0x8]; 5123 u8 reserved_0[0x18]; 5124 5125 u8 syndrome[0x20]; 5126 5127 u8 reserved_1[0x40]; 5128 5129 struct mlx5_ifc_cqc_bits cq_context; 5130 5131 u8 reserved_2[0x600]; 5132 5133 u8 pas[0][0x40]; 5134 }; 5135 5136 struct mlx5_ifc_query_cq_in_bits { 5137 u8 opcode[0x10]; 5138 u8 reserved_0[0x10]; 5139 5140 u8 reserved_1[0x10]; 5141 u8 op_mod[0x10]; 5142 5143 u8 reserved_2[0x8]; 5144 u8 cqn[0x18]; 5145 5146 u8 reserved_3[0x20]; 5147 }; 5148 5149 struct mlx5_ifc_query_cong_status_out_bits { 5150 u8 status[0x8]; 5151 u8 reserved_0[0x18]; 5152 5153 u8 syndrome[0x20]; 5154 5155 u8 reserved_1[0x20]; 5156 5157 u8 enable[0x1]; 5158 u8 tag_enable[0x1]; 5159 u8 reserved_2[0x1e]; 5160 }; 5161 5162 struct mlx5_ifc_query_cong_status_in_bits { 5163 u8 opcode[0x10]; 5164 u8 reserved_0[0x10]; 5165 5166 u8 reserved_1[0x10]; 5167 u8 op_mod[0x10]; 5168 5169 u8 reserved_2[0x18]; 5170 u8 priority[0x4]; 5171 u8 cong_protocol[0x4]; 5172 5173 u8 reserved_3[0x20]; 5174 }; 5175 5176 struct mlx5_ifc_query_cong_statistics_out_bits { 5177 u8 status[0x8]; 5178 u8 reserved_0[0x18]; 5179 5180 u8 syndrome[0x20]; 5181 5182 u8 reserved_1[0x40]; 5183 5184 u8 rp_cur_flows[0x20]; 5185 5186 u8 sum_flows[0x20]; 5187 5188 u8 rp_cnp_ignored_high[0x20]; 5189 5190 u8 rp_cnp_ignored_low[0x20]; 5191 5192 u8 rp_cnp_handled_high[0x20]; 5193 5194 u8 rp_cnp_handled_low[0x20]; 5195 5196 u8 reserved_2[0x100]; 5197 5198 u8 time_stamp_high[0x20]; 5199 5200 u8 time_stamp_low[0x20]; 5201 5202 u8 accumulators_period[0x20]; 5203 5204 u8 np_ecn_marked_roce_packets_high[0x20]; 5205 5206 u8 np_ecn_marked_roce_packets_low[0x20]; 5207 5208 u8 np_cnp_sent_high[0x20]; 5209 5210 u8 np_cnp_sent_low[0x20]; 5211 5212 u8 reserved_3[0x560]; 5213 }; 5214 5215 struct mlx5_ifc_query_cong_statistics_in_bits { 5216 u8 opcode[0x10]; 5217 u8 reserved_0[0x10]; 5218 5219 u8 reserved_1[0x10]; 5220 u8 op_mod[0x10]; 5221 5222 u8 clear[0x1]; 5223 u8 reserved_2[0x1f]; 5224 5225 u8 reserved_3[0x20]; 5226 }; 5227 5228 struct mlx5_ifc_query_cong_params_out_bits { 5229 u8 status[0x8]; 5230 u8 reserved_0[0x18]; 5231 5232 u8 syndrome[0x20]; 5233 5234 u8 reserved_1[0x40]; 5235 5236 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5237 }; 5238 5239 struct mlx5_ifc_query_cong_params_in_bits { 5240 u8 opcode[0x10]; 5241 u8 reserved_0[0x10]; 5242 5243 u8 reserved_1[0x10]; 5244 u8 op_mod[0x10]; 5245 5246 u8 reserved_2[0x1c]; 5247 u8 cong_protocol[0x4]; 5248 5249 u8 reserved_3[0x20]; 5250 }; 5251 5252 struct mlx5_ifc_query_burst_size_out_bits { 5253 u8 status[0x8]; 5254 u8 reserved_0[0x18]; 5255 5256 u8 syndrome[0x20]; 5257 5258 u8 reserved_1[0x20]; 5259 5260 u8 reserved_2[0x9]; 5261 u8 device_burst_size[0x17]; 5262 }; 5263 5264 struct mlx5_ifc_query_burst_size_in_bits { 5265 u8 opcode[0x10]; 5266 u8 reserved_0[0x10]; 5267 5268 u8 reserved_1[0x10]; 5269 u8 op_mod[0x10]; 5270 5271 u8 reserved_2[0x40]; 5272 }; 5273 5274 struct mlx5_ifc_query_adapter_out_bits { 5275 u8 status[0x8]; 5276 u8 reserved_0[0x18]; 5277 5278 u8 syndrome[0x20]; 5279 5280 u8 reserved_1[0x40]; 5281 5282 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5283 }; 5284 5285 struct mlx5_ifc_query_adapter_in_bits { 5286 u8 opcode[0x10]; 5287 u8 reserved_0[0x10]; 5288 5289 u8 reserved_1[0x10]; 5290 u8 op_mod[0x10]; 5291 5292 u8 reserved_2[0x40]; 5293 }; 5294 5295 struct mlx5_ifc_qp_2rst_out_bits { 5296 u8 status[0x8]; 5297 u8 reserved_0[0x18]; 5298 5299 u8 syndrome[0x20]; 5300 5301 u8 reserved_1[0x40]; 5302 }; 5303 5304 struct mlx5_ifc_qp_2rst_in_bits { 5305 u8 opcode[0x10]; 5306 u8 uid[0x10]; 5307 5308 u8 reserved_1[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 reserved_2[0x8]; 5312 u8 qpn[0x18]; 5313 5314 u8 reserved_3[0x20]; 5315 }; 5316 5317 struct mlx5_ifc_qp_2err_out_bits { 5318 u8 status[0x8]; 5319 u8 reserved_0[0x18]; 5320 5321 u8 syndrome[0x20]; 5322 5323 u8 reserved_1[0x40]; 5324 }; 5325 5326 struct mlx5_ifc_qp_2err_in_bits { 5327 u8 opcode[0x10]; 5328 u8 uid[0x10]; 5329 5330 u8 reserved_1[0x10]; 5331 u8 op_mod[0x10]; 5332 5333 u8 reserved_2[0x8]; 5334 u8 qpn[0x18]; 5335 5336 u8 reserved_3[0x20]; 5337 }; 5338 5339 struct mlx5_ifc_para_vport_element_bits { 5340 u8 reserved_at_0[0xc]; 5341 u8 traffic_class[0x4]; 5342 u8 qos_para_vport_number[0x10]; 5343 }; 5344 5345 struct mlx5_ifc_page_fault_resume_out_bits { 5346 u8 status[0x8]; 5347 u8 reserved_0[0x18]; 5348 5349 u8 syndrome[0x20]; 5350 5351 u8 reserved_1[0x40]; 5352 }; 5353 5354 struct mlx5_ifc_page_fault_resume_in_bits { 5355 u8 opcode[0x10]; 5356 u8 reserved_0[0x10]; 5357 5358 u8 reserved_1[0x10]; 5359 u8 op_mod[0x10]; 5360 5361 u8 error[0x1]; 5362 u8 reserved_2[0x4]; 5363 u8 rdma[0x1]; 5364 u8 read_write[0x1]; 5365 u8 req_res[0x1]; 5366 u8 qpn[0x18]; 5367 5368 u8 reserved_3[0x20]; 5369 }; 5370 5371 struct mlx5_ifc_nop_out_bits { 5372 u8 status[0x8]; 5373 u8 reserved_0[0x18]; 5374 5375 u8 syndrome[0x20]; 5376 5377 u8 reserved_1[0x40]; 5378 }; 5379 5380 struct mlx5_ifc_nop_in_bits { 5381 u8 opcode[0x10]; 5382 u8 reserved_0[0x10]; 5383 5384 u8 reserved_1[0x10]; 5385 u8 op_mod[0x10]; 5386 5387 u8 reserved_2[0x40]; 5388 }; 5389 5390 struct mlx5_ifc_modify_vport_state_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_0[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_1[0x40]; 5397 }; 5398 5399 enum { 5400 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5401 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5402 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5403 }; 5404 5405 enum { 5406 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5407 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5408 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5409 }; 5410 5411 struct mlx5_ifc_modify_vport_state_in_bits { 5412 u8 opcode[0x10]; 5413 u8 reserved_0[0x10]; 5414 5415 u8 reserved_1[0x10]; 5416 u8 op_mod[0x10]; 5417 5418 u8 other_vport[0x1]; 5419 u8 reserved_2[0xf]; 5420 u8 vport_number[0x10]; 5421 5422 u8 reserved_3[0x18]; 5423 u8 admin_state[0x4]; 5424 u8 reserved_4[0x4]; 5425 }; 5426 5427 struct mlx5_ifc_modify_tis_out_bits { 5428 u8 status[0x8]; 5429 u8 reserved_0[0x18]; 5430 5431 u8 syndrome[0x20]; 5432 5433 u8 reserved_1[0x40]; 5434 }; 5435 5436 struct mlx5_ifc_modify_tis_bitmask_bits { 5437 u8 reserved_at_0[0x20]; 5438 5439 u8 reserved_at_20[0x1d]; 5440 u8 lag_tx_port_affinity[0x1]; 5441 u8 strict_lag_tx_port_affinity[0x1]; 5442 u8 prio[0x1]; 5443 }; 5444 5445 struct mlx5_ifc_modify_tis_in_bits { 5446 u8 opcode[0x10]; 5447 u8 reserved_0[0x10]; 5448 5449 u8 reserved_1[0x10]; 5450 u8 op_mod[0x10]; 5451 5452 u8 reserved_2[0x8]; 5453 u8 tisn[0x18]; 5454 5455 u8 reserved_3[0x20]; 5456 5457 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5458 5459 u8 reserved_4[0x40]; 5460 5461 struct mlx5_ifc_tisc_bits ctx; 5462 }; 5463 5464 struct mlx5_ifc_modify_tir_out_bits { 5465 u8 status[0x8]; 5466 u8 reserved_0[0x18]; 5467 5468 u8 syndrome[0x20]; 5469 5470 u8 reserved_1[0x40]; 5471 }; 5472 5473 enum 5474 { 5475 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5476 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5477 }; 5478 5479 struct mlx5_ifc_modify_tir_in_bits { 5480 u8 opcode[0x10]; 5481 u8 reserved_0[0x10]; 5482 5483 u8 reserved_1[0x10]; 5484 u8 op_mod[0x10]; 5485 5486 u8 reserved_2[0x8]; 5487 u8 tirn[0x18]; 5488 5489 u8 reserved_3[0x20]; 5490 5491 u8 modify_bitmask[0x40]; 5492 5493 u8 reserved_4[0x40]; 5494 5495 struct mlx5_ifc_tirc_bits tir_context; 5496 }; 5497 5498 struct mlx5_ifc_modify_sq_out_bits { 5499 u8 status[0x8]; 5500 u8 reserved_0[0x18]; 5501 5502 u8 syndrome[0x20]; 5503 5504 u8 reserved_1[0x40]; 5505 }; 5506 5507 struct mlx5_ifc_modify_sq_in_bits { 5508 u8 opcode[0x10]; 5509 u8 reserved_0[0x10]; 5510 5511 u8 reserved_1[0x10]; 5512 u8 op_mod[0x10]; 5513 5514 u8 sq_state[0x4]; 5515 u8 reserved_2[0x4]; 5516 u8 sqn[0x18]; 5517 5518 u8 reserved_3[0x20]; 5519 5520 u8 modify_bitmask[0x40]; 5521 5522 u8 reserved_4[0x40]; 5523 5524 struct mlx5_ifc_sqc_bits ctx; 5525 }; 5526 5527 struct mlx5_ifc_modify_scheduling_element_out_bits { 5528 u8 status[0x8]; 5529 u8 reserved_at_8[0x18]; 5530 5531 u8 syndrome[0x20]; 5532 5533 u8 reserved_at_40[0x1c0]; 5534 }; 5535 5536 enum { 5537 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5538 }; 5539 5540 enum { 5541 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5542 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5543 }; 5544 5545 struct mlx5_ifc_modify_scheduling_element_in_bits { 5546 u8 opcode[0x10]; 5547 u8 reserved_at_10[0x10]; 5548 5549 u8 reserved_at_20[0x10]; 5550 u8 op_mod[0x10]; 5551 5552 u8 scheduling_hierarchy[0x8]; 5553 u8 reserved_at_48[0x18]; 5554 5555 u8 scheduling_element_id[0x20]; 5556 5557 u8 reserved_at_80[0x20]; 5558 5559 u8 modify_bitmask[0x20]; 5560 5561 u8 reserved_at_c0[0x40]; 5562 5563 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5564 5565 u8 reserved_at_300[0x100]; 5566 }; 5567 5568 struct mlx5_ifc_modify_rqt_out_bits { 5569 u8 status[0x8]; 5570 u8 reserved_0[0x18]; 5571 5572 u8 syndrome[0x20]; 5573 5574 u8 reserved_1[0x40]; 5575 }; 5576 5577 struct mlx5_ifc_rqt_bitmask_bits { 5578 u8 reserved_at_0[0x20]; 5579 5580 u8 reserved_at_20[0x1f]; 5581 u8 rqn_list[0x1]; 5582 }; 5583 5584 5585 struct mlx5_ifc_modify_rqt_in_bits { 5586 u8 opcode[0x10]; 5587 u8 reserved_0[0x10]; 5588 5589 u8 reserved_1[0x10]; 5590 u8 op_mod[0x10]; 5591 5592 u8 reserved_2[0x8]; 5593 u8 rqtn[0x18]; 5594 5595 u8 reserved_3[0x20]; 5596 5597 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5598 5599 u8 reserved_4[0x40]; 5600 5601 struct mlx5_ifc_rqtc_bits ctx; 5602 }; 5603 5604 struct mlx5_ifc_modify_rq_out_bits { 5605 u8 status[0x8]; 5606 u8 reserved_0[0x18]; 5607 5608 u8 syndrome[0x20]; 5609 5610 u8 reserved_1[0x40]; 5611 }; 5612 5613 enum { 5614 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5615 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5616 }; 5617 5618 struct mlx5_ifc_modify_rq_in_bits { 5619 u8 opcode[0x10]; 5620 u8 reserved_0[0x10]; 5621 5622 u8 reserved_1[0x10]; 5623 u8 op_mod[0x10]; 5624 5625 u8 rq_state[0x4]; 5626 u8 reserved_2[0x4]; 5627 u8 rqn[0x18]; 5628 5629 u8 reserved_3[0x20]; 5630 5631 u8 modify_bitmask[0x40]; 5632 5633 u8 reserved_4[0x40]; 5634 5635 struct mlx5_ifc_rqc_bits ctx; 5636 }; 5637 5638 struct mlx5_ifc_modify_rmp_out_bits { 5639 u8 status[0x8]; 5640 u8 reserved_0[0x18]; 5641 5642 u8 syndrome[0x20]; 5643 5644 u8 reserved_1[0x40]; 5645 }; 5646 5647 struct mlx5_ifc_rmp_bitmask_bits { 5648 u8 reserved[0x20]; 5649 5650 u8 reserved1[0x1f]; 5651 u8 lwm[0x1]; 5652 }; 5653 5654 struct mlx5_ifc_modify_rmp_in_bits { 5655 u8 opcode[0x10]; 5656 u8 reserved_0[0x10]; 5657 5658 u8 reserved_1[0x10]; 5659 u8 op_mod[0x10]; 5660 5661 u8 rmp_state[0x4]; 5662 u8 reserved_2[0x4]; 5663 u8 rmpn[0x18]; 5664 5665 u8 reserved_3[0x20]; 5666 5667 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5668 5669 u8 reserved_4[0x40]; 5670 5671 struct mlx5_ifc_rmpc_bits ctx; 5672 }; 5673 5674 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5675 u8 status[0x8]; 5676 u8 reserved_0[0x18]; 5677 5678 u8 syndrome[0x20]; 5679 5680 u8 reserved_1[0x40]; 5681 }; 5682 5683 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5684 u8 reserved_0[0x14]; 5685 u8 disable_uc_local_lb[0x1]; 5686 u8 disable_mc_local_lb[0x1]; 5687 u8 node_guid[0x1]; 5688 u8 port_guid[0x1]; 5689 u8 min_wqe_inline_mode[0x1]; 5690 u8 mtu[0x1]; 5691 u8 change_event[0x1]; 5692 u8 promisc[0x1]; 5693 u8 permanent_address[0x1]; 5694 u8 addresses_list[0x1]; 5695 u8 roce_en[0x1]; 5696 u8 reserved_1[0x1]; 5697 }; 5698 5699 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5700 u8 opcode[0x10]; 5701 u8 reserved_0[0x10]; 5702 5703 u8 reserved_1[0x10]; 5704 u8 op_mod[0x10]; 5705 5706 u8 other_vport[0x1]; 5707 u8 reserved_2[0xf]; 5708 u8 vport_number[0x10]; 5709 5710 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5711 5712 u8 reserved_3[0x780]; 5713 5714 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5715 }; 5716 5717 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5718 u8 status[0x8]; 5719 u8 reserved_0[0x18]; 5720 5721 u8 syndrome[0x20]; 5722 5723 u8 reserved_1[0x40]; 5724 }; 5725 5726 struct mlx5_ifc_grh_bits { 5727 u8 ip_version[4]; 5728 u8 traffic_class[8]; 5729 u8 flow_label[20]; 5730 u8 payload_length[16]; 5731 u8 next_header[8]; 5732 u8 hop_limit[8]; 5733 u8 sgid[128]; 5734 u8 dgid[128]; 5735 }; 5736 5737 struct mlx5_ifc_bth_bits { 5738 u8 opcode[8]; 5739 u8 se[1]; 5740 u8 migreq[1]; 5741 u8 pad_count[2]; 5742 u8 tver[4]; 5743 u8 p_key[16]; 5744 u8 reserved8[8]; 5745 u8 dest_qp[24]; 5746 u8 ack_req[1]; 5747 u8 reserved7[7]; 5748 u8 psn[24]; 5749 }; 5750 5751 struct mlx5_ifc_aeth_bits { 5752 u8 syndrome[8]; 5753 u8 msn[24]; 5754 }; 5755 5756 struct mlx5_ifc_dceth_bits { 5757 u8 reserved0[8]; 5758 u8 session_id[24]; 5759 u8 reserved1[8]; 5760 u8 dci_dct[24]; 5761 }; 5762 5763 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5764 u8 opcode[0x10]; 5765 u8 reserved_0[0x10]; 5766 5767 u8 reserved_1[0x10]; 5768 u8 op_mod[0x10]; 5769 5770 u8 other_vport[0x1]; 5771 u8 reserved_2[0xb]; 5772 u8 port_num[0x4]; 5773 u8 vport_number[0x10]; 5774 5775 u8 reserved_3[0x20]; 5776 5777 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5778 }; 5779 5780 struct mlx5_ifc_modify_flow_table_out_bits { 5781 u8 status[0x8]; 5782 u8 reserved_at_8[0x18]; 5783 5784 u8 syndrome[0x20]; 5785 5786 u8 reserved_at_40[0x40]; 5787 }; 5788 5789 enum { 5790 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5791 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5792 }; 5793 5794 struct mlx5_ifc_modify_flow_table_in_bits { 5795 u8 opcode[0x10]; 5796 u8 reserved_at_10[0x10]; 5797 5798 u8 reserved_at_20[0x10]; 5799 u8 op_mod[0x10]; 5800 5801 u8 other_vport[0x1]; 5802 u8 reserved_at_41[0xf]; 5803 u8 vport_number[0x10]; 5804 5805 u8 reserved_at_60[0x10]; 5806 u8 modify_field_select[0x10]; 5807 5808 u8 table_type[0x8]; 5809 u8 reserved_at_88[0x18]; 5810 5811 u8 reserved_at_a0[0x8]; 5812 u8 table_id[0x18]; 5813 5814 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5815 }; 5816 5817 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5818 u8 status[0x8]; 5819 u8 reserved_0[0x18]; 5820 5821 u8 syndrome[0x20]; 5822 5823 u8 reserved_1[0x40]; 5824 }; 5825 5826 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5827 u8 reserved[0x1c]; 5828 u8 vport_cvlan_insert[0x1]; 5829 u8 vport_svlan_insert[0x1]; 5830 u8 vport_cvlan_strip[0x1]; 5831 u8 vport_svlan_strip[0x1]; 5832 }; 5833 5834 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5835 u8 opcode[0x10]; 5836 u8 reserved_0[0x10]; 5837 5838 u8 reserved_1[0x10]; 5839 u8 op_mod[0x10]; 5840 5841 u8 other_vport[0x1]; 5842 u8 reserved_2[0xf]; 5843 u8 vport_number[0x10]; 5844 5845 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5846 5847 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5848 }; 5849 5850 struct mlx5_ifc_modify_cq_out_bits { 5851 u8 status[0x8]; 5852 u8 reserved_0[0x18]; 5853 5854 u8 syndrome[0x20]; 5855 5856 u8 reserved_1[0x40]; 5857 }; 5858 5859 enum { 5860 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5861 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5862 }; 5863 5864 struct mlx5_ifc_modify_cq_in_bits { 5865 u8 opcode[0x10]; 5866 u8 reserved_0[0x10]; 5867 5868 u8 reserved_1[0x10]; 5869 u8 op_mod[0x10]; 5870 5871 u8 reserved_2[0x8]; 5872 u8 cqn[0x18]; 5873 5874 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5875 5876 struct mlx5_ifc_cqc_bits cq_context; 5877 5878 u8 reserved_3[0x600]; 5879 5880 u8 pas[0][0x40]; 5881 }; 5882 5883 struct mlx5_ifc_modify_cong_status_out_bits { 5884 u8 status[0x8]; 5885 u8 reserved_0[0x18]; 5886 5887 u8 syndrome[0x20]; 5888 5889 u8 reserved_1[0x40]; 5890 }; 5891 5892 struct mlx5_ifc_modify_cong_status_in_bits { 5893 u8 opcode[0x10]; 5894 u8 reserved_0[0x10]; 5895 5896 u8 reserved_1[0x10]; 5897 u8 op_mod[0x10]; 5898 5899 u8 reserved_2[0x18]; 5900 u8 priority[0x4]; 5901 u8 cong_protocol[0x4]; 5902 5903 u8 enable[0x1]; 5904 u8 tag_enable[0x1]; 5905 u8 reserved_3[0x1e]; 5906 }; 5907 5908 struct mlx5_ifc_modify_cong_params_out_bits { 5909 u8 status[0x8]; 5910 u8 reserved_0[0x18]; 5911 5912 u8 syndrome[0x20]; 5913 5914 u8 reserved_1[0x40]; 5915 }; 5916 5917 struct mlx5_ifc_modify_cong_params_in_bits { 5918 u8 opcode[0x10]; 5919 u8 reserved_0[0x10]; 5920 5921 u8 reserved_1[0x10]; 5922 u8 op_mod[0x10]; 5923 5924 u8 reserved_2[0x1c]; 5925 u8 cong_protocol[0x4]; 5926 5927 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5928 5929 u8 reserved_3[0x80]; 5930 5931 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5932 }; 5933 5934 struct mlx5_ifc_manage_pages_out_bits { 5935 u8 status[0x8]; 5936 u8 reserved_0[0x18]; 5937 5938 u8 syndrome[0x20]; 5939 5940 u8 output_num_entries[0x20]; 5941 5942 u8 reserved_1[0x20]; 5943 5944 u8 pas[0][0x40]; 5945 }; 5946 5947 enum { 5948 MLX5_PAGES_CANT_GIVE = 0x0, 5949 MLX5_PAGES_GIVE = 0x1, 5950 MLX5_PAGES_TAKE = 0x2, 5951 }; 5952 5953 struct mlx5_ifc_manage_pages_in_bits { 5954 u8 opcode[0x10]; 5955 u8 reserved_0[0x10]; 5956 5957 u8 reserved_1[0x10]; 5958 u8 op_mod[0x10]; 5959 5960 u8 reserved_2[0x10]; 5961 u8 function_id[0x10]; 5962 5963 u8 input_num_entries[0x20]; 5964 5965 u8 pas[0][0x40]; 5966 }; 5967 5968 struct mlx5_ifc_mad_ifc_out_bits { 5969 u8 status[0x8]; 5970 u8 reserved_0[0x18]; 5971 5972 u8 syndrome[0x20]; 5973 5974 u8 reserved_1[0x40]; 5975 5976 u8 response_mad_packet[256][0x8]; 5977 }; 5978 5979 struct mlx5_ifc_mad_ifc_in_bits { 5980 u8 opcode[0x10]; 5981 u8 reserved_0[0x10]; 5982 5983 u8 reserved_1[0x10]; 5984 u8 op_mod[0x10]; 5985 5986 u8 remote_lid[0x10]; 5987 u8 reserved_2[0x8]; 5988 u8 port[0x8]; 5989 5990 u8 reserved_3[0x20]; 5991 5992 u8 mad[256][0x8]; 5993 }; 5994 5995 struct mlx5_ifc_init_hca_out_bits { 5996 u8 status[0x8]; 5997 u8 reserved_0[0x18]; 5998 5999 u8 syndrome[0x20]; 6000 6001 u8 reserved_1[0x40]; 6002 }; 6003 6004 enum { 6005 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 6006 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 6007 }; 6008 6009 struct mlx5_ifc_init_hca_in_bits { 6010 u8 opcode[0x10]; 6011 u8 reserved_0[0x10]; 6012 6013 u8 reserved_1[0x10]; 6014 u8 op_mod[0x10]; 6015 6016 u8 reserved_2[0x40]; 6017 }; 6018 6019 struct mlx5_ifc_init2rtr_qp_out_bits { 6020 u8 status[0x8]; 6021 u8 reserved_0[0x18]; 6022 6023 u8 syndrome[0x20]; 6024 6025 u8 reserved_1[0x40]; 6026 }; 6027 6028 struct mlx5_ifc_init2rtr_qp_in_bits { 6029 u8 opcode[0x10]; 6030 u8 uid[0x10]; 6031 6032 u8 reserved_1[0x10]; 6033 u8 op_mod[0x10]; 6034 6035 u8 reserved_2[0x8]; 6036 u8 qpn[0x18]; 6037 6038 u8 reserved_3[0x20]; 6039 6040 u8 opt_param_mask[0x20]; 6041 6042 u8 reserved_4[0x20]; 6043 6044 struct mlx5_ifc_qpc_bits qpc; 6045 6046 u8 reserved_5[0x80]; 6047 }; 6048 6049 struct mlx5_ifc_init2init_qp_out_bits { 6050 u8 status[0x8]; 6051 u8 reserved_0[0x18]; 6052 6053 u8 syndrome[0x20]; 6054 6055 u8 reserved_1[0x40]; 6056 }; 6057 6058 struct mlx5_ifc_init2init_qp_in_bits { 6059 u8 opcode[0x10]; 6060 u8 uid[0x10]; 6061 6062 u8 reserved_1[0x10]; 6063 u8 op_mod[0x10]; 6064 6065 u8 reserved_2[0x8]; 6066 u8 qpn[0x18]; 6067 6068 u8 reserved_3[0x20]; 6069 6070 u8 opt_param_mask[0x20]; 6071 6072 u8 reserved_4[0x20]; 6073 6074 struct mlx5_ifc_qpc_bits qpc; 6075 6076 u8 reserved_5[0x80]; 6077 }; 6078 6079 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6080 u8 status[0x8]; 6081 u8 reserved_0[0x18]; 6082 6083 u8 syndrome[0x20]; 6084 6085 u8 reserved_1[0x40]; 6086 6087 u8 packet_headers_log[128][0x8]; 6088 6089 u8 packet_syndrome[64][0x8]; 6090 }; 6091 6092 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6093 u8 opcode[0x10]; 6094 u8 reserved_0[0x10]; 6095 6096 u8 reserved_1[0x10]; 6097 u8 op_mod[0x10]; 6098 6099 u8 reserved_2[0x40]; 6100 }; 6101 6102 struct mlx5_ifc_encryption_key_obj_bits { 6103 u8 modify_field_select[0x40]; 6104 6105 u8 reserved_at_40[0x14]; 6106 u8 key_size[0x4]; 6107 u8 reserved_at_58[0x4]; 6108 u8 key_type[0x4]; 6109 6110 u8 reserved_at_60[0x8]; 6111 u8 pd[0x18]; 6112 6113 u8 reserved_at_80[0x180]; 6114 6115 u8 key[8][0x20]; 6116 6117 u8 reserved_at_300[0x500]; 6118 }; 6119 6120 struct mlx5_ifc_gen_eqe_in_bits { 6121 u8 opcode[0x10]; 6122 u8 reserved_0[0x10]; 6123 6124 u8 reserved_1[0x10]; 6125 u8 op_mod[0x10]; 6126 6127 u8 reserved_2[0x18]; 6128 u8 eq_number[0x8]; 6129 6130 u8 reserved_3[0x20]; 6131 6132 u8 eqe[64][0x8]; 6133 }; 6134 6135 struct mlx5_ifc_gen_eq_out_bits { 6136 u8 status[0x8]; 6137 u8 reserved_0[0x18]; 6138 6139 u8 syndrome[0x20]; 6140 6141 u8 reserved_1[0x40]; 6142 }; 6143 6144 struct mlx5_ifc_enable_hca_out_bits { 6145 u8 status[0x8]; 6146 u8 reserved_0[0x18]; 6147 6148 u8 syndrome[0x20]; 6149 6150 u8 reserved_1[0x20]; 6151 }; 6152 6153 struct mlx5_ifc_enable_hca_in_bits { 6154 u8 opcode[0x10]; 6155 u8 reserved_0[0x10]; 6156 6157 u8 reserved_1[0x10]; 6158 u8 op_mod[0x10]; 6159 6160 u8 reserved_2[0x10]; 6161 u8 function_id[0x10]; 6162 6163 u8 reserved_3[0x20]; 6164 }; 6165 6166 struct mlx5_ifc_drain_dct_out_bits { 6167 u8 status[0x8]; 6168 u8 reserved_0[0x18]; 6169 6170 u8 syndrome[0x20]; 6171 6172 u8 reserved_1[0x40]; 6173 }; 6174 6175 struct mlx5_ifc_drain_dct_in_bits { 6176 u8 opcode[0x10]; 6177 u8 uid[0x10]; 6178 6179 u8 reserved_1[0x10]; 6180 u8 op_mod[0x10]; 6181 6182 u8 reserved_2[0x8]; 6183 u8 dctn[0x18]; 6184 6185 u8 reserved_3[0x20]; 6186 }; 6187 6188 struct mlx5_ifc_disable_hca_out_bits { 6189 u8 status[0x8]; 6190 u8 reserved_0[0x18]; 6191 6192 u8 syndrome[0x20]; 6193 6194 u8 reserved_1[0x20]; 6195 }; 6196 6197 struct mlx5_ifc_disable_hca_in_bits { 6198 u8 opcode[0x10]; 6199 u8 reserved_0[0x10]; 6200 6201 u8 reserved_1[0x10]; 6202 u8 op_mod[0x10]; 6203 6204 u8 reserved_2[0x10]; 6205 u8 function_id[0x10]; 6206 6207 u8 reserved_3[0x20]; 6208 }; 6209 6210 struct mlx5_ifc_detach_from_mcg_out_bits { 6211 u8 status[0x8]; 6212 u8 reserved_0[0x18]; 6213 6214 u8 syndrome[0x20]; 6215 6216 u8 reserved_1[0x40]; 6217 }; 6218 6219 struct mlx5_ifc_detach_from_mcg_in_bits { 6220 u8 opcode[0x10]; 6221 u8 reserved_0[0x10]; 6222 6223 u8 reserved_1[0x10]; 6224 u8 op_mod[0x10]; 6225 6226 u8 reserved_2[0x8]; 6227 u8 qpn[0x18]; 6228 6229 u8 reserved_3[0x20]; 6230 6231 u8 multicast_gid[16][0x8]; 6232 }; 6233 6234 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6235 u8 status[0x8]; 6236 u8 reserved_0[0x18]; 6237 6238 u8 syndrome[0x20]; 6239 6240 u8 reserved_1[0x40]; 6241 }; 6242 6243 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6244 u8 opcode[0x10]; 6245 u8 reserved_0[0x10]; 6246 6247 u8 reserved_1[0x10]; 6248 u8 op_mod[0x10]; 6249 6250 u8 reserved_2[0x8]; 6251 u8 xrc_srqn[0x18]; 6252 6253 u8 reserved_3[0x20]; 6254 }; 6255 6256 struct mlx5_ifc_destroy_tis_out_bits { 6257 u8 status[0x8]; 6258 u8 reserved_0[0x18]; 6259 6260 u8 syndrome[0x20]; 6261 6262 u8 reserved_1[0x40]; 6263 }; 6264 6265 struct mlx5_ifc_destroy_tis_in_bits { 6266 u8 opcode[0x10]; 6267 u8 reserved_0[0x10]; 6268 6269 u8 reserved_1[0x10]; 6270 u8 op_mod[0x10]; 6271 6272 u8 reserved_2[0x8]; 6273 u8 tisn[0x18]; 6274 6275 u8 reserved_3[0x20]; 6276 }; 6277 6278 struct mlx5_ifc_destroy_tir_out_bits { 6279 u8 status[0x8]; 6280 u8 reserved_0[0x18]; 6281 6282 u8 syndrome[0x20]; 6283 6284 u8 reserved_1[0x40]; 6285 }; 6286 6287 struct mlx5_ifc_destroy_tir_in_bits { 6288 u8 opcode[0x10]; 6289 u8 reserved_0[0x10]; 6290 6291 u8 reserved_1[0x10]; 6292 u8 op_mod[0x10]; 6293 6294 u8 reserved_2[0x8]; 6295 u8 tirn[0x18]; 6296 6297 u8 reserved_3[0x20]; 6298 }; 6299 6300 struct mlx5_ifc_destroy_srq_out_bits { 6301 u8 status[0x8]; 6302 u8 reserved_0[0x18]; 6303 6304 u8 syndrome[0x20]; 6305 6306 u8 reserved_1[0x40]; 6307 }; 6308 6309 struct mlx5_ifc_destroy_srq_in_bits { 6310 u8 opcode[0x10]; 6311 u8 reserved_0[0x10]; 6312 6313 u8 reserved_1[0x10]; 6314 u8 op_mod[0x10]; 6315 6316 u8 reserved_2[0x8]; 6317 u8 srqn[0x18]; 6318 6319 u8 reserved_3[0x20]; 6320 }; 6321 6322 struct mlx5_ifc_destroy_sq_out_bits { 6323 u8 status[0x8]; 6324 u8 reserved_0[0x18]; 6325 6326 u8 syndrome[0x20]; 6327 6328 u8 reserved_1[0x40]; 6329 }; 6330 6331 struct mlx5_ifc_destroy_sq_in_bits { 6332 u8 opcode[0x10]; 6333 u8 uid[0x10]; 6334 6335 u8 reserved_1[0x10]; 6336 u8 op_mod[0x10]; 6337 6338 u8 reserved_2[0x8]; 6339 u8 sqn[0x18]; 6340 6341 u8 reserved_3[0x20]; 6342 }; 6343 6344 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6345 u8 status[0x8]; 6346 u8 reserved_at_8[0x18]; 6347 6348 u8 syndrome[0x20]; 6349 6350 u8 reserved_at_40[0x1c0]; 6351 }; 6352 6353 enum { 6354 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6355 }; 6356 6357 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6358 u8 opcode[0x10]; 6359 u8 reserved_at_10[0x10]; 6360 6361 u8 reserved_at_20[0x10]; 6362 u8 op_mod[0x10]; 6363 6364 u8 scheduling_hierarchy[0x8]; 6365 u8 reserved_at_48[0x18]; 6366 6367 u8 scheduling_element_id[0x20]; 6368 6369 u8 reserved_at_80[0x180]; 6370 }; 6371 6372 struct mlx5_ifc_destroy_rqt_out_bits { 6373 u8 status[0x8]; 6374 u8 reserved_0[0x18]; 6375 6376 u8 syndrome[0x20]; 6377 6378 u8 reserved_1[0x40]; 6379 }; 6380 6381 struct mlx5_ifc_destroy_rqt_in_bits { 6382 u8 opcode[0x10]; 6383 u8 reserved_0[0x10]; 6384 6385 u8 reserved_1[0x10]; 6386 u8 op_mod[0x10]; 6387 6388 u8 reserved_2[0x8]; 6389 u8 rqtn[0x18]; 6390 6391 u8 reserved_3[0x20]; 6392 }; 6393 6394 struct mlx5_ifc_destroy_rq_out_bits { 6395 u8 status[0x8]; 6396 u8 reserved_0[0x18]; 6397 6398 u8 syndrome[0x20]; 6399 6400 u8 reserved_1[0x40]; 6401 }; 6402 6403 struct mlx5_ifc_destroy_rq_in_bits { 6404 u8 opcode[0x10]; 6405 u8 uid[0x10]; 6406 6407 u8 reserved_1[0x10]; 6408 u8 op_mod[0x10]; 6409 6410 u8 reserved_2[0x8]; 6411 u8 rqn[0x18]; 6412 6413 u8 reserved_3[0x20]; 6414 }; 6415 6416 struct mlx5_ifc_destroy_rmp_out_bits { 6417 u8 status[0x8]; 6418 u8 reserved_0[0x18]; 6419 6420 u8 syndrome[0x20]; 6421 6422 u8 reserved_1[0x40]; 6423 }; 6424 6425 struct mlx5_ifc_destroy_rmp_in_bits { 6426 u8 opcode[0x10]; 6427 u8 reserved_0[0x10]; 6428 6429 u8 reserved_1[0x10]; 6430 u8 op_mod[0x10]; 6431 6432 u8 reserved_2[0x8]; 6433 u8 rmpn[0x18]; 6434 6435 u8 reserved_3[0x20]; 6436 }; 6437 6438 struct mlx5_ifc_destroy_qp_out_bits { 6439 u8 status[0x8]; 6440 u8 reserved_0[0x18]; 6441 6442 u8 syndrome[0x20]; 6443 6444 u8 reserved_1[0x40]; 6445 }; 6446 6447 struct mlx5_ifc_destroy_qp_in_bits { 6448 u8 opcode[0x10]; 6449 u8 uid[0x10]; 6450 6451 u8 reserved_1[0x10]; 6452 u8 op_mod[0x10]; 6453 6454 u8 reserved_2[0x8]; 6455 u8 qpn[0x18]; 6456 6457 u8 reserved_3[0x20]; 6458 }; 6459 6460 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6461 u8 status[0x8]; 6462 u8 reserved_at_8[0x18]; 6463 6464 u8 syndrome[0x20]; 6465 6466 u8 reserved_at_40[0x1c0]; 6467 }; 6468 6469 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6470 u8 opcode[0x10]; 6471 u8 reserved_at_10[0x10]; 6472 6473 u8 reserved_at_20[0x10]; 6474 u8 op_mod[0x10]; 6475 6476 u8 reserved_at_40[0x20]; 6477 6478 u8 reserved_at_60[0x10]; 6479 u8 qos_para_vport_number[0x10]; 6480 6481 u8 reserved_at_80[0x180]; 6482 }; 6483 6484 struct mlx5_ifc_destroy_psv_out_bits { 6485 u8 status[0x8]; 6486 u8 reserved_0[0x18]; 6487 6488 u8 syndrome[0x20]; 6489 6490 u8 reserved_1[0x40]; 6491 }; 6492 6493 struct mlx5_ifc_destroy_psv_in_bits { 6494 u8 opcode[0x10]; 6495 u8 reserved_0[0x10]; 6496 6497 u8 reserved_1[0x10]; 6498 u8 op_mod[0x10]; 6499 6500 u8 reserved_2[0x8]; 6501 u8 psvn[0x18]; 6502 6503 u8 reserved_3[0x20]; 6504 }; 6505 6506 struct mlx5_ifc_destroy_mkey_out_bits { 6507 u8 status[0x8]; 6508 u8 reserved_0[0x18]; 6509 6510 u8 syndrome[0x20]; 6511 6512 u8 reserved_1[0x40]; 6513 }; 6514 6515 struct mlx5_ifc_destroy_mkey_in_bits { 6516 u8 opcode[0x10]; 6517 u8 reserved_0[0x10]; 6518 6519 u8 reserved_1[0x10]; 6520 u8 op_mod[0x10]; 6521 6522 u8 reserved_2[0x8]; 6523 u8 mkey_index[0x18]; 6524 6525 u8 reserved_3[0x20]; 6526 }; 6527 6528 struct mlx5_ifc_destroy_flow_table_out_bits { 6529 u8 status[0x8]; 6530 u8 reserved_0[0x18]; 6531 6532 u8 syndrome[0x20]; 6533 6534 u8 reserved_1[0x40]; 6535 }; 6536 6537 struct mlx5_ifc_destroy_flow_table_in_bits { 6538 u8 opcode[0x10]; 6539 u8 reserved_0[0x10]; 6540 6541 u8 reserved_1[0x10]; 6542 u8 op_mod[0x10]; 6543 6544 u8 other_vport[0x1]; 6545 u8 reserved_2[0xf]; 6546 u8 vport_number[0x10]; 6547 6548 u8 reserved_3[0x20]; 6549 6550 u8 table_type[0x8]; 6551 u8 reserved_4[0x18]; 6552 6553 u8 reserved_5[0x8]; 6554 u8 table_id[0x18]; 6555 6556 u8 reserved_6[0x140]; 6557 }; 6558 6559 struct mlx5_ifc_destroy_flow_group_out_bits { 6560 u8 status[0x8]; 6561 u8 reserved_0[0x18]; 6562 6563 u8 syndrome[0x20]; 6564 6565 u8 reserved_1[0x40]; 6566 }; 6567 6568 struct mlx5_ifc_destroy_flow_group_in_bits { 6569 u8 opcode[0x10]; 6570 u8 reserved_0[0x10]; 6571 6572 u8 reserved_1[0x10]; 6573 u8 op_mod[0x10]; 6574 6575 u8 other_vport[0x1]; 6576 u8 reserved_2[0xf]; 6577 u8 vport_number[0x10]; 6578 6579 u8 reserved_3[0x20]; 6580 6581 u8 table_type[0x8]; 6582 u8 reserved_4[0x18]; 6583 6584 u8 reserved_5[0x8]; 6585 u8 table_id[0x18]; 6586 6587 u8 group_id[0x20]; 6588 6589 u8 reserved_6[0x120]; 6590 }; 6591 6592 struct mlx5_ifc_destroy_encryption_key_out_bits { 6593 u8 status[0x8]; 6594 u8 reserved_at_8[0x18]; 6595 6596 u8 syndrome[0x20]; 6597 6598 u8 reserved_at_40[0x40]; 6599 }; 6600 6601 struct mlx5_ifc_destroy_encryption_key_in_bits { 6602 u8 opcode[0x10]; 6603 u8 reserved_at_10[0x10]; 6604 6605 u8 reserved_at_20[0x10]; 6606 u8 obj_type[0x10]; 6607 6608 u8 obj_id[0x20]; 6609 6610 u8 reserved_at_60[0x20]; 6611 }; 6612 6613 struct mlx5_ifc_destroy_eq_out_bits { 6614 u8 status[0x8]; 6615 u8 reserved_0[0x18]; 6616 6617 u8 syndrome[0x20]; 6618 6619 u8 reserved_1[0x40]; 6620 }; 6621 6622 struct mlx5_ifc_destroy_eq_in_bits { 6623 u8 opcode[0x10]; 6624 u8 reserved_0[0x10]; 6625 6626 u8 reserved_1[0x10]; 6627 u8 op_mod[0x10]; 6628 6629 u8 reserved_2[0x18]; 6630 u8 eq_number[0x8]; 6631 6632 u8 reserved_3[0x20]; 6633 }; 6634 6635 struct mlx5_ifc_destroy_dct_out_bits { 6636 u8 status[0x8]; 6637 u8 reserved_0[0x18]; 6638 6639 u8 syndrome[0x20]; 6640 6641 u8 reserved_1[0x40]; 6642 }; 6643 6644 struct mlx5_ifc_destroy_dct_in_bits { 6645 u8 opcode[0x10]; 6646 u8 uid[0x10]; 6647 6648 u8 reserved_1[0x10]; 6649 u8 op_mod[0x10]; 6650 6651 u8 reserved_2[0x8]; 6652 u8 dctn[0x18]; 6653 6654 u8 reserved_3[0x20]; 6655 }; 6656 6657 struct mlx5_ifc_destroy_cq_out_bits { 6658 u8 status[0x8]; 6659 u8 reserved_0[0x18]; 6660 6661 u8 syndrome[0x20]; 6662 6663 u8 reserved_1[0x40]; 6664 }; 6665 6666 struct mlx5_ifc_destroy_cq_in_bits { 6667 u8 opcode[0x10]; 6668 u8 reserved_0[0x10]; 6669 6670 u8 reserved_1[0x10]; 6671 u8 op_mod[0x10]; 6672 6673 u8 reserved_2[0x8]; 6674 u8 cqn[0x18]; 6675 6676 u8 reserved_3[0x20]; 6677 }; 6678 6679 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6680 u8 status[0x8]; 6681 u8 reserved_0[0x18]; 6682 6683 u8 syndrome[0x20]; 6684 6685 u8 reserved_1[0x40]; 6686 }; 6687 6688 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6689 u8 opcode[0x10]; 6690 u8 reserved_0[0x10]; 6691 6692 u8 reserved_1[0x10]; 6693 u8 op_mod[0x10]; 6694 6695 u8 reserved_2[0x20]; 6696 6697 u8 reserved_3[0x10]; 6698 u8 vxlan_udp_port[0x10]; 6699 }; 6700 6701 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6702 u8 status[0x8]; 6703 u8 reserved_0[0x18]; 6704 6705 u8 syndrome[0x20]; 6706 6707 u8 reserved_1[0x40]; 6708 }; 6709 6710 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6711 u8 opcode[0x10]; 6712 u8 reserved_0[0x10]; 6713 6714 u8 reserved_1[0x10]; 6715 u8 op_mod[0x10]; 6716 6717 u8 reserved_2[0x60]; 6718 6719 u8 reserved_3[0x8]; 6720 u8 table_index[0x18]; 6721 6722 u8 reserved_4[0x140]; 6723 }; 6724 6725 struct mlx5_ifc_delete_fte_out_bits { 6726 u8 status[0x8]; 6727 u8 reserved_0[0x18]; 6728 6729 u8 syndrome[0x20]; 6730 6731 u8 reserved_1[0x40]; 6732 }; 6733 6734 struct mlx5_ifc_delete_fte_in_bits { 6735 u8 opcode[0x10]; 6736 u8 reserved_0[0x10]; 6737 6738 u8 reserved_1[0x10]; 6739 u8 op_mod[0x10]; 6740 6741 u8 other_vport[0x1]; 6742 u8 reserved_2[0xf]; 6743 u8 vport_number[0x10]; 6744 6745 u8 reserved_3[0x20]; 6746 6747 u8 table_type[0x8]; 6748 u8 reserved_4[0x18]; 6749 6750 u8 reserved_5[0x8]; 6751 u8 table_id[0x18]; 6752 6753 u8 reserved_6[0x40]; 6754 6755 u8 flow_index[0x20]; 6756 6757 u8 reserved_7[0xe0]; 6758 }; 6759 6760 struct mlx5_ifc_dealloc_xrcd_out_bits { 6761 u8 status[0x8]; 6762 u8 reserved_0[0x18]; 6763 6764 u8 syndrome[0x20]; 6765 6766 u8 reserved_1[0x40]; 6767 }; 6768 6769 struct mlx5_ifc_dealloc_xrcd_in_bits { 6770 u8 opcode[0x10]; 6771 u8 reserved_0[0x10]; 6772 6773 u8 reserved_1[0x10]; 6774 u8 op_mod[0x10]; 6775 6776 u8 reserved_2[0x8]; 6777 u8 xrcd[0x18]; 6778 6779 u8 reserved_3[0x20]; 6780 }; 6781 6782 struct mlx5_ifc_dealloc_uar_out_bits { 6783 u8 status[0x8]; 6784 u8 reserved_0[0x18]; 6785 6786 u8 syndrome[0x20]; 6787 6788 u8 reserved_1[0x40]; 6789 }; 6790 6791 struct mlx5_ifc_dealloc_uar_in_bits { 6792 u8 opcode[0x10]; 6793 u8 reserved_0[0x10]; 6794 6795 u8 reserved_1[0x10]; 6796 u8 op_mod[0x10]; 6797 6798 u8 reserved_2[0x8]; 6799 u8 uar[0x18]; 6800 6801 u8 reserved_3[0x20]; 6802 }; 6803 6804 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6805 u8 status[0x8]; 6806 u8 reserved_0[0x18]; 6807 6808 u8 syndrome[0x20]; 6809 6810 u8 reserved_1[0x40]; 6811 }; 6812 6813 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6814 u8 opcode[0x10]; 6815 u8 reserved_0[0x10]; 6816 6817 u8 reserved_1[0x10]; 6818 u8 op_mod[0x10]; 6819 6820 u8 reserved_2[0x8]; 6821 u8 transport_domain[0x18]; 6822 6823 u8 reserved_3[0x20]; 6824 }; 6825 6826 struct mlx5_ifc_dealloc_q_counter_out_bits { 6827 u8 status[0x8]; 6828 u8 reserved_0[0x18]; 6829 6830 u8 syndrome[0x20]; 6831 6832 u8 reserved_1[0x40]; 6833 }; 6834 6835 struct mlx5_ifc_counter_id_bits { 6836 u8 reserved[0x10]; 6837 u8 counter_id[0x10]; 6838 }; 6839 6840 struct mlx5_ifc_diagnostic_params_context_bits { 6841 u8 num_of_counters[0x10]; 6842 u8 reserved_2[0x8]; 6843 u8 log_num_of_samples[0x8]; 6844 6845 u8 single[0x1]; 6846 u8 repetitive[0x1]; 6847 u8 sync[0x1]; 6848 u8 clear[0x1]; 6849 u8 on_demand[0x1]; 6850 u8 enable[0x1]; 6851 u8 reserved_3[0x12]; 6852 u8 log_sample_period[0x8]; 6853 6854 u8 reserved_4[0x80]; 6855 6856 struct mlx5_ifc_counter_id_bits counter_id[0]; 6857 }; 6858 6859 struct mlx5_ifc_set_diagnostic_params_in_bits { 6860 u8 opcode[0x10]; 6861 u8 reserved_0[0x10]; 6862 6863 u8 reserved_1[0x10]; 6864 u8 op_mod[0x10]; 6865 6866 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6867 }; 6868 6869 struct mlx5_ifc_set_diagnostic_params_out_bits { 6870 u8 status[0x8]; 6871 u8 reserved_0[0x18]; 6872 6873 u8 syndrome[0x20]; 6874 6875 u8 reserved_1[0x40]; 6876 }; 6877 6878 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6879 u8 opcode[0x10]; 6880 u8 reserved_0[0x10]; 6881 6882 u8 reserved_1[0x10]; 6883 u8 op_mod[0x10]; 6884 6885 u8 num_of_samples[0x10]; 6886 u8 sample_index[0x10]; 6887 6888 u8 reserved_2[0x20]; 6889 }; 6890 6891 struct mlx5_ifc_diagnostic_counter_bits { 6892 u8 counter_id[0x10]; 6893 u8 sample_id[0x10]; 6894 6895 u8 time_stamp_31_0[0x20]; 6896 6897 u8 counter_value_h[0x20]; 6898 6899 u8 counter_value_l[0x20]; 6900 }; 6901 6902 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6903 u8 status[0x8]; 6904 u8 reserved_0[0x18]; 6905 6906 u8 syndrome[0x20]; 6907 6908 u8 reserved_1[0x40]; 6909 6910 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6911 }; 6912 6913 struct mlx5_ifc_dealloc_q_counter_in_bits { 6914 u8 opcode[0x10]; 6915 u8 reserved_0[0x10]; 6916 6917 u8 reserved_1[0x10]; 6918 u8 op_mod[0x10]; 6919 6920 u8 reserved_2[0x18]; 6921 u8 counter_set_id[0x8]; 6922 6923 u8 reserved_3[0x20]; 6924 }; 6925 6926 struct mlx5_ifc_dealloc_pd_out_bits { 6927 u8 status[0x8]; 6928 u8 reserved_0[0x18]; 6929 6930 u8 syndrome[0x20]; 6931 6932 u8 reserved_1[0x40]; 6933 }; 6934 6935 struct mlx5_ifc_dealloc_pd_in_bits { 6936 u8 opcode[0x10]; 6937 u8 reserved_0[0x10]; 6938 6939 u8 reserved_1[0x10]; 6940 u8 op_mod[0x10]; 6941 6942 u8 reserved_2[0x8]; 6943 u8 pd[0x18]; 6944 6945 u8 reserved_3[0x20]; 6946 }; 6947 6948 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6949 u8 status[0x8]; 6950 u8 reserved_0[0x18]; 6951 6952 u8 syndrome[0x20]; 6953 6954 u8 reserved_1[0x40]; 6955 }; 6956 6957 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6958 u8 opcode[0x10]; 6959 u8 reserved_0[0x10]; 6960 6961 u8 reserved_1[0x10]; 6962 u8 op_mod[0x10]; 6963 6964 u8 reserved_2[0x10]; 6965 u8 flow_counter_id[0x10]; 6966 6967 u8 reserved_3[0x20]; 6968 }; 6969 6970 struct mlx5_ifc_deactivate_tracer_out_bits { 6971 u8 status[0x8]; 6972 u8 reserved_0[0x18]; 6973 6974 u8 syndrome[0x20]; 6975 6976 u8 reserved_1[0x40]; 6977 }; 6978 6979 struct mlx5_ifc_deactivate_tracer_in_bits { 6980 u8 opcode[0x10]; 6981 u8 reserved_0[0x10]; 6982 6983 u8 reserved_1[0x10]; 6984 u8 op_mod[0x10]; 6985 6986 u8 mkey[0x20]; 6987 6988 u8 reserved_2[0x20]; 6989 }; 6990 6991 struct mlx5_ifc_create_xrc_srq_out_bits { 6992 u8 status[0x8]; 6993 u8 reserved_0[0x18]; 6994 6995 u8 syndrome[0x20]; 6996 6997 u8 reserved_1[0x8]; 6998 u8 xrc_srqn[0x18]; 6999 7000 u8 reserved_2[0x20]; 7001 }; 7002 7003 struct mlx5_ifc_create_xrc_srq_in_bits { 7004 u8 opcode[0x10]; 7005 u8 reserved_0[0x10]; 7006 7007 u8 reserved_1[0x10]; 7008 u8 op_mod[0x10]; 7009 7010 u8 reserved_2[0x40]; 7011 7012 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7013 7014 u8 reserved_3[0x600]; 7015 7016 u8 pas[0][0x40]; 7017 }; 7018 7019 struct mlx5_ifc_create_tis_out_bits { 7020 u8 status[0x8]; 7021 u8 reserved_0[0x18]; 7022 7023 u8 syndrome[0x20]; 7024 7025 u8 reserved_1[0x8]; 7026 u8 tisn[0x18]; 7027 7028 u8 reserved_2[0x20]; 7029 }; 7030 7031 struct mlx5_ifc_create_tis_in_bits { 7032 u8 opcode[0x10]; 7033 u8 reserved_0[0x10]; 7034 7035 u8 reserved_1[0x10]; 7036 u8 op_mod[0x10]; 7037 7038 u8 reserved_2[0xc0]; 7039 7040 struct mlx5_ifc_tisc_bits ctx; 7041 }; 7042 7043 struct mlx5_ifc_create_tir_out_bits { 7044 u8 status[0x8]; 7045 u8 reserved_0[0x18]; 7046 7047 u8 syndrome[0x20]; 7048 7049 u8 reserved_1[0x8]; 7050 u8 tirn[0x18]; 7051 7052 u8 reserved_2[0x20]; 7053 }; 7054 7055 struct mlx5_ifc_create_tir_in_bits { 7056 u8 opcode[0x10]; 7057 u8 reserved_0[0x10]; 7058 7059 u8 reserved_1[0x10]; 7060 u8 op_mod[0x10]; 7061 7062 u8 reserved_2[0xc0]; 7063 7064 struct mlx5_ifc_tirc_bits tir_context; 7065 }; 7066 7067 struct mlx5_ifc_create_srq_out_bits { 7068 u8 status[0x8]; 7069 u8 reserved_0[0x18]; 7070 7071 u8 syndrome[0x20]; 7072 7073 u8 reserved_1[0x8]; 7074 u8 srqn[0x18]; 7075 7076 u8 reserved_2[0x20]; 7077 }; 7078 7079 struct mlx5_ifc_create_srq_in_bits { 7080 u8 opcode[0x10]; 7081 u8 reserved_0[0x10]; 7082 7083 u8 reserved_1[0x10]; 7084 u8 op_mod[0x10]; 7085 7086 u8 reserved_2[0x40]; 7087 7088 struct mlx5_ifc_srqc_bits srq_context_entry; 7089 7090 u8 reserved_3[0x600]; 7091 7092 u8 pas[0][0x40]; 7093 }; 7094 7095 struct mlx5_ifc_create_sq_out_bits { 7096 u8 status[0x8]; 7097 u8 reserved_0[0x18]; 7098 7099 u8 syndrome[0x20]; 7100 7101 u8 reserved_1[0x8]; 7102 u8 sqn[0x18]; 7103 7104 u8 reserved_2[0x20]; 7105 }; 7106 7107 struct mlx5_ifc_create_sq_in_bits { 7108 u8 opcode[0x10]; 7109 u8 uid[0x10]; 7110 7111 u8 reserved_1[0x10]; 7112 u8 op_mod[0x10]; 7113 7114 u8 reserved_2[0xc0]; 7115 7116 struct mlx5_ifc_sqc_bits ctx; 7117 }; 7118 7119 struct mlx5_ifc_create_scheduling_element_out_bits { 7120 u8 status[0x8]; 7121 u8 reserved_at_8[0x18]; 7122 7123 u8 syndrome[0x20]; 7124 7125 u8 reserved_at_40[0x40]; 7126 7127 u8 scheduling_element_id[0x20]; 7128 7129 u8 reserved_at_a0[0x160]; 7130 }; 7131 7132 enum { 7133 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7134 }; 7135 7136 struct mlx5_ifc_create_scheduling_element_in_bits { 7137 u8 opcode[0x10]; 7138 u8 reserved_at_10[0x10]; 7139 7140 u8 reserved_at_20[0x10]; 7141 u8 op_mod[0x10]; 7142 7143 u8 scheduling_hierarchy[0x8]; 7144 u8 reserved_at_48[0x18]; 7145 7146 u8 reserved_at_60[0xa0]; 7147 7148 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7149 7150 u8 reserved_at_300[0x100]; 7151 }; 7152 7153 struct mlx5_ifc_create_rqt_out_bits { 7154 u8 status[0x8]; 7155 u8 reserved_0[0x18]; 7156 7157 u8 syndrome[0x20]; 7158 7159 u8 reserved_1[0x8]; 7160 u8 rqtn[0x18]; 7161 7162 u8 reserved_2[0x20]; 7163 }; 7164 7165 struct mlx5_ifc_create_rqt_in_bits { 7166 u8 opcode[0x10]; 7167 u8 reserved_0[0x10]; 7168 7169 u8 reserved_1[0x10]; 7170 u8 op_mod[0x10]; 7171 7172 u8 reserved_2[0xc0]; 7173 7174 struct mlx5_ifc_rqtc_bits rqt_context; 7175 }; 7176 7177 struct mlx5_ifc_create_rq_out_bits { 7178 u8 status[0x8]; 7179 u8 reserved_0[0x18]; 7180 7181 u8 syndrome[0x20]; 7182 7183 u8 reserved_1[0x8]; 7184 u8 rqn[0x18]; 7185 7186 u8 reserved_2[0x20]; 7187 }; 7188 7189 struct mlx5_ifc_create_rq_in_bits { 7190 u8 opcode[0x10]; 7191 u8 uid[0x10]; 7192 7193 u8 reserved_1[0x10]; 7194 u8 op_mod[0x10]; 7195 7196 u8 reserved_2[0xc0]; 7197 7198 struct mlx5_ifc_rqc_bits ctx; 7199 }; 7200 7201 struct mlx5_ifc_create_rmp_out_bits { 7202 u8 status[0x8]; 7203 u8 reserved_0[0x18]; 7204 7205 u8 syndrome[0x20]; 7206 7207 u8 reserved_1[0x8]; 7208 u8 rmpn[0x18]; 7209 7210 u8 reserved_2[0x20]; 7211 }; 7212 7213 struct mlx5_ifc_create_rmp_in_bits { 7214 u8 opcode[0x10]; 7215 u8 reserved_0[0x10]; 7216 7217 u8 reserved_1[0x10]; 7218 u8 op_mod[0x10]; 7219 7220 u8 reserved_2[0xc0]; 7221 7222 struct mlx5_ifc_rmpc_bits ctx; 7223 }; 7224 7225 struct mlx5_ifc_create_qp_out_bits { 7226 u8 status[0x8]; 7227 u8 reserved_0[0x18]; 7228 7229 u8 syndrome[0x20]; 7230 7231 u8 reserved_1[0x8]; 7232 u8 qpn[0x18]; 7233 7234 u8 reserved_2[0x20]; 7235 }; 7236 7237 struct mlx5_ifc_create_qp_in_bits { 7238 u8 opcode[0x10]; 7239 u8 uid[0x10]; 7240 7241 u8 reserved_1[0x10]; 7242 u8 op_mod[0x10]; 7243 7244 u8 reserved_2[0x8]; 7245 u8 input_qpn[0x18]; 7246 7247 u8 reserved_3[0x20]; 7248 7249 u8 opt_param_mask[0x20]; 7250 7251 u8 reserved_4[0x20]; 7252 7253 struct mlx5_ifc_qpc_bits qpc; 7254 7255 u8 reserved_5[0x80]; 7256 7257 u8 pas[0][0x40]; 7258 }; 7259 7260 struct mlx5_ifc_create_qos_para_vport_out_bits { 7261 u8 status[0x8]; 7262 u8 reserved_at_8[0x18]; 7263 7264 u8 syndrome[0x20]; 7265 7266 u8 reserved_at_40[0x20]; 7267 7268 u8 reserved_at_60[0x10]; 7269 u8 qos_para_vport_number[0x10]; 7270 7271 u8 reserved_at_80[0x180]; 7272 }; 7273 7274 struct mlx5_ifc_create_qos_para_vport_in_bits { 7275 u8 opcode[0x10]; 7276 u8 reserved_at_10[0x10]; 7277 7278 u8 reserved_at_20[0x10]; 7279 u8 op_mod[0x10]; 7280 7281 u8 reserved_at_40[0x1c0]; 7282 }; 7283 7284 struct mlx5_ifc_create_psv_out_bits { 7285 u8 status[0x8]; 7286 u8 reserved_0[0x18]; 7287 7288 u8 syndrome[0x20]; 7289 7290 u8 reserved_1[0x40]; 7291 7292 u8 reserved_2[0x8]; 7293 u8 psv0_index[0x18]; 7294 7295 u8 reserved_3[0x8]; 7296 u8 psv1_index[0x18]; 7297 7298 u8 reserved_4[0x8]; 7299 u8 psv2_index[0x18]; 7300 7301 u8 reserved_5[0x8]; 7302 u8 psv3_index[0x18]; 7303 }; 7304 7305 struct mlx5_ifc_create_psv_in_bits { 7306 u8 opcode[0x10]; 7307 u8 reserved_0[0x10]; 7308 7309 u8 reserved_1[0x10]; 7310 u8 op_mod[0x10]; 7311 7312 u8 num_psv[0x4]; 7313 u8 reserved_2[0x4]; 7314 u8 pd[0x18]; 7315 7316 u8 reserved_3[0x20]; 7317 }; 7318 7319 struct mlx5_ifc_create_mkey_out_bits { 7320 u8 status[0x8]; 7321 u8 reserved_0[0x18]; 7322 7323 u8 syndrome[0x20]; 7324 7325 u8 reserved_1[0x8]; 7326 u8 mkey_index[0x18]; 7327 7328 u8 reserved_2[0x20]; 7329 }; 7330 7331 struct mlx5_ifc_create_mkey_in_bits { 7332 u8 opcode[0x10]; 7333 u8 reserved_0[0x10]; 7334 7335 u8 reserved_1[0x10]; 7336 u8 op_mod[0x10]; 7337 7338 u8 reserved_2[0x20]; 7339 7340 u8 pg_access[0x1]; 7341 u8 reserved_3[0x1f]; 7342 7343 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7344 7345 u8 reserved_4[0x80]; 7346 7347 u8 translations_octword_actual_size[0x20]; 7348 7349 u8 reserved_5[0x560]; 7350 7351 u8 klm_pas_mtt[0][0x20]; 7352 }; 7353 7354 struct mlx5_ifc_create_flow_table_out_bits { 7355 u8 status[0x8]; 7356 u8 reserved_0[0x18]; 7357 7358 u8 syndrome[0x20]; 7359 7360 u8 reserved_1[0x8]; 7361 u8 table_id[0x18]; 7362 7363 u8 reserved_2[0x20]; 7364 }; 7365 7366 struct mlx5_ifc_create_flow_table_in_bits { 7367 u8 opcode[0x10]; 7368 u8 reserved_at_10[0x10]; 7369 7370 u8 reserved_at_20[0x10]; 7371 u8 op_mod[0x10]; 7372 7373 u8 other_vport[0x1]; 7374 u8 reserved_at_41[0xf]; 7375 u8 vport_number[0x10]; 7376 7377 u8 reserved_at_60[0x20]; 7378 7379 u8 table_type[0x8]; 7380 u8 reserved_at_88[0x18]; 7381 7382 u8 reserved_at_a0[0x20]; 7383 7384 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7385 }; 7386 7387 struct mlx5_ifc_create_flow_group_out_bits { 7388 u8 status[0x8]; 7389 u8 reserved_0[0x18]; 7390 7391 u8 syndrome[0x20]; 7392 7393 u8 reserved_1[0x8]; 7394 u8 group_id[0x18]; 7395 7396 u8 reserved_2[0x20]; 7397 }; 7398 7399 enum { 7400 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7401 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7402 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7403 }; 7404 7405 struct mlx5_ifc_create_flow_group_in_bits { 7406 u8 opcode[0x10]; 7407 u8 reserved_0[0x10]; 7408 7409 u8 reserved_1[0x10]; 7410 u8 op_mod[0x10]; 7411 7412 u8 other_vport[0x1]; 7413 u8 reserved_2[0xf]; 7414 u8 vport_number[0x10]; 7415 7416 u8 reserved_3[0x20]; 7417 7418 u8 table_type[0x8]; 7419 u8 reserved_4[0x18]; 7420 7421 u8 reserved_5[0x8]; 7422 u8 table_id[0x18]; 7423 7424 u8 reserved_6[0x20]; 7425 7426 u8 start_flow_index[0x20]; 7427 7428 u8 reserved_7[0x20]; 7429 7430 u8 end_flow_index[0x20]; 7431 7432 u8 reserved_8[0xa0]; 7433 7434 u8 reserved_9[0x18]; 7435 u8 match_criteria_enable[0x8]; 7436 7437 struct mlx5_ifc_fte_match_param_bits match_criteria; 7438 7439 u8 reserved_10[0xe00]; 7440 }; 7441 7442 struct mlx5_ifc_create_encryption_key_out_bits { 7443 u8 status[0x8]; 7444 u8 reserved_at_8[0x18]; 7445 7446 u8 syndrome[0x20]; 7447 7448 u8 obj_id[0x20]; 7449 7450 u8 reserved_at_60[0x20]; 7451 }; 7452 7453 struct mlx5_ifc_create_encryption_key_in_bits { 7454 u8 opcode[0x10]; 7455 u8 reserved_at_10[0x10]; 7456 7457 u8 reserved_at_20[0x10]; 7458 u8 obj_type[0x10]; 7459 7460 u8 reserved_at_40[0x40]; 7461 7462 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 7463 }; 7464 7465 struct mlx5_ifc_create_eq_out_bits { 7466 u8 status[0x8]; 7467 u8 reserved_0[0x18]; 7468 7469 u8 syndrome[0x20]; 7470 7471 u8 reserved_1[0x18]; 7472 u8 eq_number[0x8]; 7473 7474 u8 reserved_2[0x20]; 7475 }; 7476 7477 struct mlx5_ifc_create_eq_in_bits { 7478 u8 opcode[0x10]; 7479 u8 reserved_0[0x10]; 7480 7481 u8 reserved_1[0x10]; 7482 u8 op_mod[0x10]; 7483 7484 u8 reserved_2[0x40]; 7485 7486 struct mlx5_ifc_eqc_bits eq_context_entry; 7487 7488 u8 reserved_3[0x40]; 7489 7490 u8 event_bitmask[0x40]; 7491 7492 u8 reserved_4[0x580]; 7493 7494 u8 pas[0][0x40]; 7495 }; 7496 7497 struct mlx5_ifc_create_dct_out_bits { 7498 u8 status[0x8]; 7499 u8 reserved_0[0x18]; 7500 7501 u8 syndrome[0x20]; 7502 7503 u8 reserved_1[0x8]; 7504 u8 dctn[0x18]; 7505 7506 u8 reserved_2[0x20]; 7507 }; 7508 7509 struct mlx5_ifc_create_dct_in_bits { 7510 u8 opcode[0x10]; 7511 u8 uid[0x10]; 7512 7513 u8 reserved_1[0x10]; 7514 u8 op_mod[0x10]; 7515 7516 u8 reserved_2[0x40]; 7517 7518 struct mlx5_ifc_dctc_bits dct_context_entry; 7519 7520 u8 reserved_3[0x180]; 7521 }; 7522 7523 struct mlx5_ifc_create_cq_out_bits { 7524 u8 status[0x8]; 7525 u8 reserved_0[0x18]; 7526 7527 u8 syndrome[0x20]; 7528 7529 u8 reserved_1[0x8]; 7530 u8 cqn[0x18]; 7531 7532 u8 reserved_2[0x20]; 7533 }; 7534 7535 struct mlx5_ifc_create_cq_in_bits { 7536 u8 opcode[0x10]; 7537 u8 reserved_0[0x10]; 7538 7539 u8 reserved_1[0x10]; 7540 u8 op_mod[0x10]; 7541 7542 u8 reserved_2[0x40]; 7543 7544 struct mlx5_ifc_cqc_bits cq_context; 7545 7546 u8 reserved_3[0x600]; 7547 7548 u8 pas[0][0x40]; 7549 }; 7550 7551 struct mlx5_ifc_config_int_moderation_out_bits { 7552 u8 status[0x8]; 7553 u8 reserved_0[0x18]; 7554 7555 u8 syndrome[0x20]; 7556 7557 u8 reserved_1[0x4]; 7558 u8 min_delay[0xc]; 7559 u8 int_vector[0x10]; 7560 7561 u8 reserved_2[0x20]; 7562 }; 7563 7564 enum { 7565 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7566 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7567 }; 7568 7569 struct mlx5_ifc_config_int_moderation_in_bits { 7570 u8 opcode[0x10]; 7571 u8 reserved_0[0x10]; 7572 7573 u8 reserved_1[0x10]; 7574 u8 op_mod[0x10]; 7575 7576 u8 reserved_2[0x4]; 7577 u8 min_delay[0xc]; 7578 u8 int_vector[0x10]; 7579 7580 u8 reserved_3[0x20]; 7581 }; 7582 7583 struct mlx5_ifc_attach_to_mcg_out_bits { 7584 u8 status[0x8]; 7585 u8 reserved_0[0x18]; 7586 7587 u8 syndrome[0x20]; 7588 7589 u8 reserved_1[0x40]; 7590 }; 7591 7592 struct mlx5_ifc_attach_to_mcg_in_bits { 7593 u8 opcode[0x10]; 7594 u8 reserved_0[0x10]; 7595 7596 u8 reserved_1[0x10]; 7597 u8 op_mod[0x10]; 7598 7599 u8 reserved_2[0x8]; 7600 u8 qpn[0x18]; 7601 7602 u8 reserved_3[0x20]; 7603 7604 u8 multicast_gid[16][0x8]; 7605 }; 7606 7607 struct mlx5_ifc_arm_xrc_srq_out_bits { 7608 u8 status[0x8]; 7609 u8 reserved_0[0x18]; 7610 7611 u8 syndrome[0x20]; 7612 7613 u8 reserved_1[0x40]; 7614 }; 7615 7616 enum { 7617 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7618 }; 7619 7620 struct mlx5_ifc_arm_xrc_srq_in_bits { 7621 u8 opcode[0x10]; 7622 u8 reserved_0[0x10]; 7623 7624 u8 reserved_1[0x10]; 7625 u8 op_mod[0x10]; 7626 7627 u8 reserved_2[0x8]; 7628 u8 xrc_srqn[0x18]; 7629 7630 u8 reserved_3[0x10]; 7631 u8 lwm[0x10]; 7632 }; 7633 7634 struct mlx5_ifc_arm_rq_out_bits { 7635 u8 status[0x8]; 7636 u8 reserved_0[0x18]; 7637 7638 u8 syndrome[0x20]; 7639 7640 u8 reserved_1[0x40]; 7641 }; 7642 7643 enum { 7644 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7645 }; 7646 7647 struct mlx5_ifc_arm_rq_in_bits { 7648 u8 opcode[0x10]; 7649 u8 reserved_0[0x10]; 7650 7651 u8 reserved_1[0x10]; 7652 u8 op_mod[0x10]; 7653 7654 u8 reserved_2[0x8]; 7655 u8 srq_number[0x18]; 7656 7657 u8 reserved_3[0x10]; 7658 u8 lwm[0x10]; 7659 }; 7660 7661 struct mlx5_ifc_arm_dct_out_bits { 7662 u8 status[0x8]; 7663 u8 reserved_0[0x18]; 7664 7665 u8 syndrome[0x20]; 7666 7667 u8 reserved_1[0x40]; 7668 }; 7669 7670 struct mlx5_ifc_arm_dct_in_bits { 7671 u8 opcode[0x10]; 7672 u8 reserved_0[0x10]; 7673 7674 u8 reserved_1[0x10]; 7675 u8 op_mod[0x10]; 7676 7677 u8 reserved_2[0x8]; 7678 u8 dctn[0x18]; 7679 7680 u8 reserved_3[0x20]; 7681 }; 7682 7683 struct mlx5_ifc_alloc_xrcd_out_bits { 7684 u8 status[0x8]; 7685 u8 reserved_0[0x18]; 7686 7687 u8 syndrome[0x20]; 7688 7689 u8 reserved_1[0x8]; 7690 u8 xrcd[0x18]; 7691 7692 u8 reserved_2[0x20]; 7693 }; 7694 7695 struct mlx5_ifc_alloc_xrcd_in_bits { 7696 u8 opcode[0x10]; 7697 u8 reserved_0[0x10]; 7698 7699 u8 reserved_1[0x10]; 7700 u8 op_mod[0x10]; 7701 7702 u8 reserved_2[0x40]; 7703 }; 7704 7705 struct mlx5_ifc_alloc_uar_out_bits { 7706 u8 status[0x8]; 7707 u8 reserved_0[0x18]; 7708 7709 u8 syndrome[0x20]; 7710 7711 u8 reserved_1[0x8]; 7712 u8 uar[0x18]; 7713 7714 u8 reserved_2[0x20]; 7715 }; 7716 7717 struct mlx5_ifc_alloc_uar_in_bits { 7718 u8 opcode[0x10]; 7719 u8 reserved_0[0x10]; 7720 7721 u8 reserved_1[0x10]; 7722 u8 op_mod[0x10]; 7723 7724 u8 reserved_2[0x40]; 7725 }; 7726 7727 struct mlx5_ifc_alloc_transport_domain_out_bits { 7728 u8 status[0x8]; 7729 u8 reserved_0[0x18]; 7730 7731 u8 syndrome[0x20]; 7732 7733 u8 reserved_1[0x8]; 7734 u8 transport_domain[0x18]; 7735 7736 u8 reserved_2[0x20]; 7737 }; 7738 7739 struct mlx5_ifc_alloc_transport_domain_in_bits { 7740 u8 opcode[0x10]; 7741 u8 reserved_0[0x10]; 7742 7743 u8 reserved_1[0x10]; 7744 u8 op_mod[0x10]; 7745 7746 u8 reserved_2[0x40]; 7747 }; 7748 7749 struct mlx5_ifc_alloc_q_counter_out_bits { 7750 u8 status[0x8]; 7751 u8 reserved_0[0x18]; 7752 7753 u8 syndrome[0x20]; 7754 7755 u8 reserved_1[0x18]; 7756 u8 counter_set_id[0x8]; 7757 7758 u8 reserved_2[0x20]; 7759 }; 7760 7761 struct mlx5_ifc_alloc_q_counter_in_bits { 7762 u8 opcode[0x10]; 7763 u8 reserved_0[0x10]; 7764 7765 u8 reserved_1[0x10]; 7766 u8 op_mod[0x10]; 7767 7768 u8 reserved_2[0x40]; 7769 }; 7770 7771 struct mlx5_ifc_alloc_pd_out_bits { 7772 u8 status[0x8]; 7773 u8 reserved_0[0x18]; 7774 7775 u8 syndrome[0x20]; 7776 7777 u8 reserved_1[0x8]; 7778 u8 pd[0x18]; 7779 7780 u8 reserved_2[0x20]; 7781 }; 7782 7783 struct mlx5_ifc_alloc_pd_in_bits { 7784 u8 opcode[0x10]; 7785 u8 reserved_0[0x10]; 7786 7787 u8 reserved_1[0x10]; 7788 u8 op_mod[0x10]; 7789 7790 u8 reserved_2[0x40]; 7791 }; 7792 7793 struct mlx5_ifc_alloc_flow_counter_out_bits { 7794 u8 status[0x8]; 7795 u8 reserved_0[0x18]; 7796 7797 u8 syndrome[0x20]; 7798 7799 u8 reserved_1[0x10]; 7800 u8 flow_counter_id[0x10]; 7801 7802 u8 reserved_2[0x20]; 7803 }; 7804 7805 struct mlx5_ifc_alloc_flow_counter_in_bits { 7806 u8 opcode[0x10]; 7807 u8 reserved_0[0x10]; 7808 7809 u8 reserved_1[0x10]; 7810 u8 op_mod[0x10]; 7811 7812 u8 reserved_2[0x40]; 7813 }; 7814 7815 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7816 u8 status[0x8]; 7817 u8 reserved_0[0x18]; 7818 7819 u8 syndrome[0x20]; 7820 7821 u8 reserved_1[0x40]; 7822 }; 7823 7824 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7825 u8 opcode[0x10]; 7826 u8 reserved_0[0x10]; 7827 7828 u8 reserved_1[0x10]; 7829 u8 op_mod[0x10]; 7830 7831 u8 reserved_2[0x20]; 7832 7833 u8 reserved_3[0x10]; 7834 u8 vxlan_udp_port[0x10]; 7835 }; 7836 7837 struct mlx5_ifc_activate_tracer_out_bits { 7838 u8 status[0x8]; 7839 u8 reserved_0[0x18]; 7840 7841 u8 syndrome[0x20]; 7842 7843 u8 reserved_1[0x40]; 7844 }; 7845 7846 struct mlx5_ifc_activate_tracer_in_bits { 7847 u8 opcode[0x10]; 7848 u8 reserved_0[0x10]; 7849 7850 u8 reserved_1[0x10]; 7851 u8 op_mod[0x10]; 7852 7853 u8 mkey[0x20]; 7854 7855 u8 reserved_2[0x20]; 7856 }; 7857 7858 struct mlx5_ifc_set_rate_limit_out_bits { 7859 u8 status[0x8]; 7860 u8 reserved_at_8[0x18]; 7861 7862 u8 syndrome[0x20]; 7863 7864 u8 reserved_at_40[0x40]; 7865 }; 7866 7867 struct mlx5_ifc_set_rate_limit_in_bits { 7868 u8 opcode[0x10]; 7869 u8 reserved_at_10[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 reserved_at_40[0x10]; 7875 u8 rate_limit_index[0x10]; 7876 7877 u8 reserved_at_60[0x20]; 7878 7879 u8 rate_limit[0x20]; 7880 7881 u8 burst_upper_bound[0x20]; 7882 7883 u8 reserved_at_c0[0x10]; 7884 u8 typical_packet_size[0x10]; 7885 7886 u8 reserved_at_e0[0x120]; 7887 }; 7888 7889 struct mlx5_ifc_access_register_out_bits { 7890 u8 status[0x8]; 7891 u8 reserved_0[0x18]; 7892 7893 u8 syndrome[0x20]; 7894 7895 u8 reserved_1[0x40]; 7896 7897 u8 register_data[0][0x20]; 7898 }; 7899 7900 enum { 7901 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7902 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7903 }; 7904 7905 struct mlx5_ifc_access_register_in_bits { 7906 u8 opcode[0x10]; 7907 u8 reserved_0[0x10]; 7908 7909 u8 reserved_1[0x10]; 7910 u8 op_mod[0x10]; 7911 7912 u8 reserved_2[0x10]; 7913 u8 register_id[0x10]; 7914 7915 u8 argument[0x20]; 7916 7917 u8 register_data[0][0x20]; 7918 }; 7919 7920 struct mlx5_ifc_sltp_reg_bits { 7921 u8 status[0x4]; 7922 u8 version[0x4]; 7923 u8 local_port[0x8]; 7924 u8 pnat[0x2]; 7925 u8 reserved_0[0x2]; 7926 u8 lane[0x4]; 7927 u8 reserved_1[0x8]; 7928 7929 u8 reserved_2[0x20]; 7930 7931 u8 reserved_3[0x7]; 7932 u8 polarity[0x1]; 7933 u8 ob_tap0[0x8]; 7934 u8 ob_tap1[0x8]; 7935 u8 ob_tap2[0x8]; 7936 7937 u8 reserved_4[0xc]; 7938 u8 ob_preemp_mode[0x4]; 7939 u8 ob_reg[0x8]; 7940 u8 ob_bias[0x8]; 7941 7942 u8 reserved_5[0x20]; 7943 }; 7944 7945 struct mlx5_ifc_slrp_reg_bits { 7946 u8 status[0x4]; 7947 u8 version[0x4]; 7948 u8 local_port[0x8]; 7949 u8 pnat[0x2]; 7950 u8 reserved_0[0x2]; 7951 u8 lane[0x4]; 7952 u8 reserved_1[0x8]; 7953 7954 u8 ib_sel[0x2]; 7955 u8 reserved_2[0x11]; 7956 u8 dp_sel[0x1]; 7957 u8 dp90sel[0x4]; 7958 u8 mix90phase[0x8]; 7959 7960 u8 ffe_tap0[0x8]; 7961 u8 ffe_tap1[0x8]; 7962 u8 ffe_tap2[0x8]; 7963 u8 ffe_tap3[0x8]; 7964 7965 u8 ffe_tap4[0x8]; 7966 u8 ffe_tap5[0x8]; 7967 u8 ffe_tap6[0x8]; 7968 u8 ffe_tap7[0x8]; 7969 7970 u8 ffe_tap8[0x8]; 7971 u8 mixerbias_tap_amp[0x8]; 7972 u8 reserved_3[0x7]; 7973 u8 ffe_tap_en[0x9]; 7974 7975 u8 ffe_tap_offset0[0x8]; 7976 u8 ffe_tap_offset1[0x8]; 7977 u8 slicer_offset0[0x10]; 7978 7979 u8 mixer_offset0[0x10]; 7980 u8 mixer_offset1[0x10]; 7981 7982 u8 mixerbgn_inp[0x8]; 7983 u8 mixerbgn_inn[0x8]; 7984 u8 mixerbgn_refp[0x8]; 7985 u8 mixerbgn_refn[0x8]; 7986 7987 u8 sel_slicer_lctrl_h[0x1]; 7988 u8 sel_slicer_lctrl_l[0x1]; 7989 u8 reserved_4[0x1]; 7990 u8 ref_mixer_vreg[0x5]; 7991 u8 slicer_gctrl[0x8]; 7992 u8 lctrl_input[0x8]; 7993 u8 mixer_offset_cm1[0x8]; 7994 7995 u8 common_mode[0x6]; 7996 u8 reserved_5[0x1]; 7997 u8 mixer_offset_cm0[0x9]; 7998 u8 reserved_6[0x7]; 7999 u8 slicer_offset_cm[0x9]; 8000 }; 8001 8002 struct mlx5_ifc_slrg_reg_bits { 8003 u8 status[0x4]; 8004 u8 version[0x4]; 8005 u8 local_port[0x8]; 8006 u8 pnat[0x2]; 8007 u8 reserved_0[0x2]; 8008 u8 lane[0x4]; 8009 u8 reserved_1[0x8]; 8010 8011 u8 time_to_link_up[0x10]; 8012 u8 reserved_2[0xc]; 8013 u8 grade_lane_speed[0x4]; 8014 8015 u8 grade_version[0x8]; 8016 u8 grade[0x18]; 8017 8018 u8 reserved_3[0x4]; 8019 u8 height_grade_type[0x4]; 8020 u8 height_grade[0x18]; 8021 8022 u8 height_dz[0x10]; 8023 u8 height_dv[0x10]; 8024 8025 u8 reserved_4[0x10]; 8026 u8 height_sigma[0x10]; 8027 8028 u8 reserved_5[0x20]; 8029 8030 u8 reserved_6[0x4]; 8031 u8 phase_grade_type[0x4]; 8032 u8 phase_grade[0x18]; 8033 8034 u8 reserved_7[0x8]; 8035 u8 phase_eo_pos[0x8]; 8036 u8 reserved_8[0x8]; 8037 u8 phase_eo_neg[0x8]; 8038 8039 u8 ffe_set_tested[0x10]; 8040 u8 test_errors_per_lane[0x10]; 8041 }; 8042 8043 struct mlx5_ifc_pvlc_reg_bits { 8044 u8 reserved_0[0x8]; 8045 u8 local_port[0x8]; 8046 u8 reserved_1[0x10]; 8047 8048 u8 reserved_2[0x1c]; 8049 u8 vl_hw_cap[0x4]; 8050 8051 u8 reserved_3[0x1c]; 8052 u8 vl_admin[0x4]; 8053 8054 u8 reserved_4[0x1c]; 8055 u8 vl_operational[0x4]; 8056 }; 8057 8058 struct mlx5_ifc_pude_reg_bits { 8059 u8 swid[0x8]; 8060 u8 local_port[0x8]; 8061 u8 reserved_0[0x4]; 8062 u8 admin_status[0x4]; 8063 u8 reserved_1[0x4]; 8064 u8 oper_status[0x4]; 8065 8066 u8 reserved_2[0x60]; 8067 }; 8068 8069 enum { 8070 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 8071 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 8072 }; 8073 8074 struct mlx5_ifc_ptys_reg_bits { 8075 u8 reserved_0[0x1]; 8076 u8 an_disable_admin[0x1]; 8077 u8 an_disable_cap[0x1]; 8078 u8 reserved_1[0x4]; 8079 u8 force_tx_aba_param[0x1]; 8080 u8 local_port[0x8]; 8081 u8 reserved_2[0xd]; 8082 u8 proto_mask[0x3]; 8083 8084 u8 an_status[0x4]; 8085 u8 reserved_3[0xc]; 8086 u8 data_rate_oper[0x10]; 8087 8088 u8 ext_eth_proto_capability[0x20]; 8089 8090 u8 eth_proto_capability[0x20]; 8091 8092 u8 ib_link_width_capability[0x10]; 8093 u8 ib_proto_capability[0x10]; 8094 8095 u8 ext_eth_proto_admin[0x20]; 8096 8097 u8 eth_proto_admin[0x20]; 8098 8099 u8 ib_link_width_admin[0x10]; 8100 u8 ib_proto_admin[0x10]; 8101 8102 u8 ext_eth_proto_oper[0x20]; 8103 8104 u8 eth_proto_oper[0x20]; 8105 8106 u8 ib_link_width_oper[0x10]; 8107 u8 ib_proto_oper[0x10]; 8108 8109 u8 reserved_4[0x1c]; 8110 u8 connector_type[0x4]; 8111 8112 u8 eth_proto_lp_advertise[0x20]; 8113 8114 u8 reserved_5[0x60]; 8115 }; 8116 8117 struct mlx5_ifc_ptas_reg_bits { 8118 u8 reserved_0[0x20]; 8119 8120 u8 algorithm_options[0x10]; 8121 u8 reserved_1[0x4]; 8122 u8 repetitions_mode[0x4]; 8123 u8 num_of_repetitions[0x8]; 8124 8125 u8 grade_version[0x8]; 8126 u8 height_grade_type[0x4]; 8127 u8 phase_grade_type[0x4]; 8128 u8 height_grade_weight[0x8]; 8129 u8 phase_grade_weight[0x8]; 8130 8131 u8 gisim_measure_bits[0x10]; 8132 u8 adaptive_tap_measure_bits[0x10]; 8133 8134 u8 ber_bath_high_error_threshold[0x10]; 8135 u8 ber_bath_mid_error_threshold[0x10]; 8136 8137 u8 ber_bath_low_error_threshold[0x10]; 8138 u8 one_ratio_high_threshold[0x10]; 8139 8140 u8 one_ratio_high_mid_threshold[0x10]; 8141 u8 one_ratio_low_mid_threshold[0x10]; 8142 8143 u8 one_ratio_low_threshold[0x10]; 8144 u8 ndeo_error_threshold[0x10]; 8145 8146 u8 mixer_offset_step_size[0x10]; 8147 u8 reserved_2[0x8]; 8148 u8 mix90_phase_for_voltage_bath[0x8]; 8149 8150 u8 mixer_offset_start[0x10]; 8151 u8 mixer_offset_end[0x10]; 8152 8153 u8 reserved_3[0x15]; 8154 u8 ber_test_time[0xb]; 8155 }; 8156 8157 struct mlx5_ifc_pspa_reg_bits { 8158 u8 swid[0x8]; 8159 u8 local_port[0x8]; 8160 u8 sub_port[0x8]; 8161 u8 reserved_0[0x8]; 8162 8163 u8 reserved_1[0x20]; 8164 }; 8165 8166 struct mlx5_ifc_ppsc_reg_bits { 8167 u8 reserved_0[0x8]; 8168 u8 local_port[0x8]; 8169 u8 reserved_1[0x10]; 8170 8171 u8 reserved_2[0x60]; 8172 8173 u8 reserved_3[0x1c]; 8174 u8 wrps_admin[0x4]; 8175 8176 u8 reserved_4[0x1c]; 8177 u8 wrps_status[0x4]; 8178 8179 u8 up_th_vld[0x1]; 8180 u8 down_th_vld[0x1]; 8181 u8 reserved_5[0x6]; 8182 u8 up_threshold[0x8]; 8183 u8 reserved_6[0x8]; 8184 u8 down_threshold[0x8]; 8185 8186 u8 reserved_7[0x20]; 8187 8188 u8 reserved_8[0x1c]; 8189 u8 srps_admin[0x4]; 8190 8191 u8 reserved_9[0x60]; 8192 }; 8193 8194 struct mlx5_ifc_pplr_reg_bits { 8195 u8 reserved_0[0x8]; 8196 u8 local_port[0x8]; 8197 u8 reserved_1[0x10]; 8198 8199 u8 reserved_2[0x8]; 8200 u8 lb_cap[0x8]; 8201 u8 reserved_3[0x8]; 8202 u8 lb_en[0x8]; 8203 }; 8204 8205 struct mlx5_ifc_pplm_reg_bits { 8206 u8 reserved_at_0[0x8]; 8207 u8 local_port[0x8]; 8208 u8 reserved_at_10[0x10]; 8209 8210 u8 reserved_at_20[0x20]; 8211 8212 u8 port_profile_mode[0x8]; 8213 u8 static_port_profile[0x8]; 8214 u8 active_port_profile[0x8]; 8215 u8 reserved_at_58[0x8]; 8216 8217 u8 retransmission_active[0x8]; 8218 u8 fec_mode_active[0x18]; 8219 8220 u8 rs_fec_correction_bypass_cap[0x4]; 8221 u8 reserved_at_84[0x8]; 8222 u8 fec_override_cap_56g[0x4]; 8223 u8 fec_override_cap_100g[0x4]; 8224 u8 fec_override_cap_50g[0x4]; 8225 u8 fec_override_cap_25g[0x4]; 8226 u8 fec_override_cap_10g_40g[0x4]; 8227 8228 u8 rs_fec_correction_bypass_admin[0x4]; 8229 u8 reserved_at_a4[0x8]; 8230 u8 fec_override_admin_56g[0x4]; 8231 u8 fec_override_admin_100g[0x4]; 8232 u8 fec_override_admin_50g[0x4]; 8233 u8 fec_override_admin_25g[0x4]; 8234 u8 fec_override_admin_10g_40g[0x4]; 8235 8236 u8 fec_override_cap_400g_8x[0x10]; 8237 u8 fec_override_cap_200g_4x[0x10]; 8238 u8 fec_override_cap_100g_2x[0x10]; 8239 u8 fec_override_cap_50g_1x[0x10]; 8240 8241 u8 fec_override_admin_400g_8x[0x10]; 8242 u8 fec_override_admin_200g_4x[0x10]; 8243 u8 fec_override_admin_100g_2x[0x10]; 8244 u8 fec_override_admin_50g_1x[0x10]; 8245 8246 u8 reserved_at_140[0x140]; 8247 }; 8248 8249 struct mlx5_ifc_ppll_reg_bits { 8250 u8 num_pll_groups[0x8]; 8251 u8 pll_group[0x8]; 8252 u8 reserved_0[0x4]; 8253 u8 num_plls[0x4]; 8254 u8 reserved_1[0x8]; 8255 8256 u8 reserved_2[0x1f]; 8257 u8 ae[0x1]; 8258 8259 u8 pll_status[4][0x40]; 8260 }; 8261 8262 struct mlx5_ifc_ppad_reg_bits { 8263 u8 reserved_0[0x3]; 8264 u8 single_mac[0x1]; 8265 u8 reserved_1[0x4]; 8266 u8 local_port[0x8]; 8267 u8 mac_47_32[0x10]; 8268 8269 u8 mac_31_0[0x20]; 8270 8271 u8 reserved_2[0x40]; 8272 }; 8273 8274 struct mlx5_ifc_pmtu_reg_bits { 8275 u8 reserved_0[0x8]; 8276 u8 local_port[0x8]; 8277 u8 reserved_1[0x10]; 8278 8279 u8 max_mtu[0x10]; 8280 u8 reserved_2[0x10]; 8281 8282 u8 admin_mtu[0x10]; 8283 u8 reserved_3[0x10]; 8284 8285 u8 oper_mtu[0x10]; 8286 u8 reserved_4[0x10]; 8287 }; 8288 8289 struct mlx5_ifc_pmpr_reg_bits { 8290 u8 reserved_0[0x8]; 8291 u8 module[0x8]; 8292 u8 reserved_1[0x10]; 8293 8294 u8 reserved_2[0x18]; 8295 u8 attenuation_5g[0x8]; 8296 8297 u8 reserved_3[0x18]; 8298 u8 attenuation_7g[0x8]; 8299 8300 u8 reserved_4[0x18]; 8301 u8 attenuation_12g[0x8]; 8302 }; 8303 8304 struct mlx5_ifc_pmpe_reg_bits { 8305 u8 reserved_0[0x8]; 8306 u8 module[0x8]; 8307 u8 reserved_1[0xc]; 8308 u8 module_status[0x4]; 8309 8310 u8 reserved_2[0x14]; 8311 u8 error_type[0x4]; 8312 u8 reserved_3[0x8]; 8313 8314 u8 reserved_4[0x40]; 8315 }; 8316 8317 struct mlx5_ifc_pmpc_reg_bits { 8318 u8 module_state_updated[32][0x8]; 8319 }; 8320 8321 struct mlx5_ifc_pmlpn_reg_bits { 8322 u8 reserved_0[0x4]; 8323 u8 mlpn_status[0x4]; 8324 u8 local_port[0x8]; 8325 u8 reserved_1[0x10]; 8326 8327 u8 e[0x1]; 8328 u8 reserved_2[0x1f]; 8329 }; 8330 8331 struct mlx5_ifc_pmlp_reg_bits { 8332 u8 rxtx[0x1]; 8333 u8 reserved_0[0x7]; 8334 u8 local_port[0x8]; 8335 u8 reserved_1[0x8]; 8336 u8 width[0x8]; 8337 8338 u8 lane0_module_mapping[0x20]; 8339 8340 u8 lane1_module_mapping[0x20]; 8341 8342 u8 lane2_module_mapping[0x20]; 8343 8344 u8 lane3_module_mapping[0x20]; 8345 8346 u8 reserved_2[0x160]; 8347 }; 8348 8349 struct mlx5_ifc_pmaos_reg_bits { 8350 u8 reserved_0[0x8]; 8351 u8 module[0x8]; 8352 u8 reserved_1[0x4]; 8353 u8 admin_status[0x4]; 8354 u8 reserved_2[0x4]; 8355 u8 oper_status[0x4]; 8356 8357 u8 ase[0x1]; 8358 u8 ee[0x1]; 8359 u8 reserved_3[0x12]; 8360 u8 error_type[0x4]; 8361 u8 reserved_4[0x6]; 8362 u8 e[0x2]; 8363 8364 u8 reserved_5[0x40]; 8365 }; 8366 8367 struct mlx5_ifc_plpc_reg_bits { 8368 u8 reserved_0[0x4]; 8369 u8 profile_id[0xc]; 8370 u8 reserved_1[0x4]; 8371 u8 proto_mask[0x4]; 8372 u8 reserved_2[0x8]; 8373 8374 u8 reserved_3[0x10]; 8375 u8 lane_speed[0x10]; 8376 8377 u8 reserved_4[0x17]; 8378 u8 lpbf[0x1]; 8379 u8 fec_mode_policy[0x8]; 8380 8381 u8 retransmission_capability[0x8]; 8382 u8 fec_mode_capability[0x18]; 8383 8384 u8 retransmission_support_admin[0x8]; 8385 u8 fec_mode_support_admin[0x18]; 8386 8387 u8 retransmission_request_admin[0x8]; 8388 u8 fec_mode_request_admin[0x18]; 8389 8390 u8 reserved_5[0x80]; 8391 }; 8392 8393 struct mlx5_ifc_pll_status_data_bits { 8394 u8 reserved_0[0x1]; 8395 u8 lock_cal[0x1]; 8396 u8 lock_status[0x2]; 8397 u8 reserved_1[0x2]; 8398 u8 algo_f_ctrl[0xa]; 8399 u8 analog_algo_num_var[0x6]; 8400 u8 f_ctrl_measure[0xa]; 8401 8402 u8 reserved_2[0x2]; 8403 u8 analog_var[0x6]; 8404 u8 reserved_3[0x2]; 8405 u8 high_var[0x6]; 8406 u8 reserved_4[0x2]; 8407 u8 low_var[0x6]; 8408 u8 reserved_5[0x2]; 8409 u8 mid_val[0x6]; 8410 }; 8411 8412 struct mlx5_ifc_plib_reg_bits { 8413 u8 reserved_0[0x8]; 8414 u8 local_port[0x8]; 8415 u8 reserved_1[0x8]; 8416 u8 ib_port[0x8]; 8417 8418 u8 reserved_2[0x60]; 8419 }; 8420 8421 struct mlx5_ifc_plbf_reg_bits { 8422 u8 reserved_0[0x8]; 8423 u8 local_port[0x8]; 8424 u8 reserved_1[0xd]; 8425 u8 lbf_mode[0x3]; 8426 8427 u8 reserved_2[0x20]; 8428 }; 8429 8430 struct mlx5_ifc_pipg_reg_bits { 8431 u8 reserved_0[0x8]; 8432 u8 local_port[0x8]; 8433 u8 reserved_1[0x10]; 8434 8435 u8 dic[0x1]; 8436 u8 reserved_2[0x19]; 8437 u8 ipg[0x4]; 8438 u8 reserved_3[0x2]; 8439 }; 8440 8441 struct mlx5_ifc_pifr_reg_bits { 8442 u8 reserved_0[0x8]; 8443 u8 local_port[0x8]; 8444 u8 reserved_1[0x10]; 8445 8446 u8 reserved_2[0xe0]; 8447 8448 u8 port_filter[8][0x20]; 8449 8450 u8 port_filter_update_en[8][0x20]; 8451 }; 8452 8453 struct mlx5_ifc_phys_layer_cntrs_bits { 8454 u8 time_since_last_clear_high[0x20]; 8455 8456 u8 time_since_last_clear_low[0x20]; 8457 8458 u8 symbol_errors_high[0x20]; 8459 8460 u8 symbol_errors_low[0x20]; 8461 8462 u8 sync_headers_errors_high[0x20]; 8463 8464 u8 sync_headers_errors_low[0x20]; 8465 8466 u8 edpl_bip_errors_lane0_high[0x20]; 8467 8468 u8 edpl_bip_errors_lane0_low[0x20]; 8469 8470 u8 edpl_bip_errors_lane1_high[0x20]; 8471 8472 u8 edpl_bip_errors_lane1_low[0x20]; 8473 8474 u8 edpl_bip_errors_lane2_high[0x20]; 8475 8476 u8 edpl_bip_errors_lane2_low[0x20]; 8477 8478 u8 edpl_bip_errors_lane3_high[0x20]; 8479 8480 u8 edpl_bip_errors_lane3_low[0x20]; 8481 8482 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8483 8484 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8485 8486 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8487 8488 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8489 8490 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8491 8492 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8493 8494 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8495 8496 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8497 8498 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8499 8500 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8501 8502 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8503 8504 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8505 8506 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8507 8508 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8509 8510 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8511 8512 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8513 8514 u8 rs_fec_corrected_blocks_high[0x20]; 8515 8516 u8 rs_fec_corrected_blocks_low[0x20]; 8517 8518 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8519 8520 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8521 8522 u8 rs_fec_no_errors_blocks_high[0x20]; 8523 8524 u8 rs_fec_no_errors_blocks_low[0x20]; 8525 8526 u8 rs_fec_single_error_blocks_high[0x20]; 8527 8528 u8 rs_fec_single_error_blocks_low[0x20]; 8529 8530 u8 rs_fec_corrected_symbols_total_high[0x20]; 8531 8532 u8 rs_fec_corrected_symbols_total_low[0x20]; 8533 8534 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8535 8536 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8537 8538 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8539 8540 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8541 8542 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8543 8544 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8545 8546 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8547 8548 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8549 8550 u8 link_down_events[0x20]; 8551 8552 u8 successful_recovery_events[0x20]; 8553 8554 u8 reserved_0[0x180]; 8555 }; 8556 8557 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8558 u8 symbol_error_counter[0x10]; 8559 8560 u8 link_error_recovery_counter[0x8]; 8561 8562 u8 link_downed_counter[0x8]; 8563 8564 u8 port_rcv_errors[0x10]; 8565 8566 u8 port_rcv_remote_physical_errors[0x10]; 8567 8568 u8 port_rcv_switch_relay_errors[0x10]; 8569 8570 u8 port_xmit_discards[0x10]; 8571 8572 u8 port_xmit_constraint_errors[0x8]; 8573 8574 u8 port_rcv_constraint_errors[0x8]; 8575 8576 u8 reserved_at_70[0x8]; 8577 8578 u8 link_overrun_errors[0x8]; 8579 8580 u8 reserved_at_80[0x10]; 8581 8582 u8 vl_15_dropped[0x10]; 8583 8584 u8 reserved_at_a0[0xa0]; 8585 }; 8586 8587 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8588 u8 time_since_last_clear_high[0x20]; 8589 8590 u8 time_since_last_clear_low[0x20]; 8591 8592 u8 phy_received_bits_high[0x20]; 8593 8594 u8 phy_received_bits_low[0x20]; 8595 8596 u8 phy_symbol_errors_high[0x20]; 8597 8598 u8 phy_symbol_errors_low[0x20]; 8599 8600 u8 phy_corrected_bits_high[0x20]; 8601 8602 u8 phy_corrected_bits_low[0x20]; 8603 8604 u8 phy_corrected_bits_lane0_high[0x20]; 8605 8606 u8 phy_corrected_bits_lane0_low[0x20]; 8607 8608 u8 phy_corrected_bits_lane1_high[0x20]; 8609 8610 u8 phy_corrected_bits_lane1_low[0x20]; 8611 8612 u8 phy_corrected_bits_lane2_high[0x20]; 8613 8614 u8 phy_corrected_bits_lane2_low[0x20]; 8615 8616 u8 phy_corrected_bits_lane3_high[0x20]; 8617 8618 u8 phy_corrected_bits_lane3_low[0x20]; 8619 8620 u8 reserved_at_200[0x5c0]; 8621 }; 8622 8623 struct mlx5_ifc_infiniband_port_cntrs_bits { 8624 u8 symbol_error_counter[0x10]; 8625 u8 link_error_recovery_counter[0x8]; 8626 u8 link_downed_counter[0x8]; 8627 8628 u8 port_rcv_errors[0x10]; 8629 u8 port_rcv_remote_physical_errors[0x10]; 8630 8631 u8 port_rcv_switch_relay_errors[0x10]; 8632 u8 port_xmit_discards[0x10]; 8633 8634 u8 port_xmit_constraint_errors[0x8]; 8635 u8 port_rcv_constraint_errors[0x8]; 8636 u8 reserved_0[0x8]; 8637 u8 local_link_integrity_errors[0x4]; 8638 u8 excessive_buffer_overrun_errors[0x4]; 8639 8640 u8 reserved_1[0x10]; 8641 u8 vl_15_dropped[0x10]; 8642 8643 u8 port_xmit_data[0x20]; 8644 8645 u8 port_rcv_data[0x20]; 8646 8647 u8 port_xmit_pkts[0x20]; 8648 8649 u8 port_rcv_pkts[0x20]; 8650 8651 u8 port_xmit_wait[0x20]; 8652 8653 u8 reserved_2[0x680]; 8654 }; 8655 8656 struct mlx5_ifc_phrr_reg_bits { 8657 u8 clr[0x1]; 8658 u8 reserved_0[0x7]; 8659 u8 local_port[0x8]; 8660 u8 reserved_1[0x10]; 8661 8662 u8 hist_group[0x8]; 8663 u8 reserved_2[0x10]; 8664 u8 hist_id[0x8]; 8665 8666 u8 reserved_3[0x40]; 8667 8668 u8 time_since_last_clear_high[0x20]; 8669 8670 u8 time_since_last_clear_low[0x20]; 8671 8672 u8 bin[10][0x20]; 8673 }; 8674 8675 struct mlx5_ifc_phbr_for_prio_reg_bits { 8676 u8 reserved_0[0x18]; 8677 u8 prio[0x8]; 8678 }; 8679 8680 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8681 u8 reserved_0[0x18]; 8682 u8 tclass[0x8]; 8683 }; 8684 8685 struct mlx5_ifc_phbr_binding_reg_bits { 8686 u8 opcode[0x4]; 8687 u8 reserved_0[0x4]; 8688 u8 local_port[0x8]; 8689 u8 pnat[0x2]; 8690 u8 reserved_1[0xe]; 8691 8692 u8 hist_group[0x8]; 8693 u8 reserved_2[0x10]; 8694 u8 hist_id[0x8]; 8695 8696 u8 reserved_3[0x10]; 8697 u8 hist_type[0x10]; 8698 8699 u8 hist_parameters[0x20]; 8700 8701 u8 hist_min_value[0x20]; 8702 8703 u8 hist_max_value[0x20]; 8704 8705 u8 sample_time[0x20]; 8706 }; 8707 8708 enum { 8709 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8710 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8711 }; 8712 8713 struct mlx5_ifc_pfcc_reg_bits { 8714 u8 dcbx_operation_type[0x2]; 8715 u8 cap_local_admin[0x1]; 8716 u8 cap_remote_admin[0x1]; 8717 u8 reserved_0[0x4]; 8718 u8 local_port[0x8]; 8719 u8 pnat[0x2]; 8720 u8 reserved_1[0xc]; 8721 u8 shl_cap[0x1]; 8722 u8 shl_opr[0x1]; 8723 8724 u8 ppan[0x4]; 8725 u8 reserved_2[0x4]; 8726 u8 prio_mask_tx[0x8]; 8727 u8 reserved_3[0x8]; 8728 u8 prio_mask_rx[0x8]; 8729 8730 u8 pptx[0x1]; 8731 u8 aptx[0x1]; 8732 u8 reserved_4[0x6]; 8733 u8 pfctx[0x8]; 8734 u8 reserved_5[0x8]; 8735 u8 cbftx[0x8]; 8736 8737 u8 pprx[0x1]; 8738 u8 aprx[0x1]; 8739 u8 reserved_6[0x6]; 8740 u8 pfcrx[0x8]; 8741 u8 reserved_7[0x8]; 8742 u8 cbfrx[0x8]; 8743 8744 u8 device_stall_minor_watermark[0x10]; 8745 u8 device_stall_critical_watermark[0x10]; 8746 8747 u8 reserved_8[0x60]; 8748 }; 8749 8750 struct mlx5_ifc_pelc_reg_bits { 8751 u8 op[0x4]; 8752 u8 reserved_0[0x4]; 8753 u8 local_port[0x8]; 8754 u8 reserved_1[0x10]; 8755 8756 u8 op_admin[0x8]; 8757 u8 op_capability[0x8]; 8758 u8 op_request[0x8]; 8759 u8 op_active[0x8]; 8760 8761 u8 admin[0x40]; 8762 8763 u8 capability[0x40]; 8764 8765 u8 request[0x40]; 8766 8767 u8 active[0x40]; 8768 8769 u8 reserved_2[0x80]; 8770 }; 8771 8772 struct mlx5_ifc_peir_reg_bits { 8773 u8 reserved_0[0x8]; 8774 u8 local_port[0x8]; 8775 u8 reserved_1[0x10]; 8776 8777 u8 reserved_2[0xc]; 8778 u8 error_count[0x4]; 8779 u8 reserved_3[0x10]; 8780 8781 u8 reserved_4[0xc]; 8782 u8 lane[0x4]; 8783 u8 reserved_5[0x8]; 8784 u8 error_type[0x8]; 8785 }; 8786 8787 struct mlx5_ifc_qcam_access_reg_cap_mask { 8788 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8789 u8 qpdpm[0x1]; 8790 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8791 u8 qdpm[0x1]; 8792 u8 qpts[0x1]; 8793 u8 qcap[0x1]; 8794 u8 qcam_access_reg_cap_mask_0[0x1]; 8795 }; 8796 8797 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8798 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8799 u8 qpts_trust_both[0x1]; 8800 }; 8801 8802 struct mlx5_ifc_qcam_reg_bits { 8803 u8 reserved_at_0[0x8]; 8804 u8 feature_group[0x8]; 8805 u8 reserved_at_10[0x8]; 8806 u8 access_reg_group[0x8]; 8807 u8 reserved_at_20[0x20]; 8808 8809 union { 8810 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8811 u8 reserved_at_0[0x80]; 8812 } qos_access_reg_cap_mask; 8813 8814 u8 reserved_at_c0[0x80]; 8815 8816 union { 8817 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8818 u8 reserved_at_0[0x80]; 8819 } qos_feature_cap_mask; 8820 8821 u8 reserved_at_1c0[0x80]; 8822 }; 8823 8824 struct mlx5_ifc_pcam_enhanced_features_bits { 8825 u8 reserved_at_0[0x6d]; 8826 u8 rx_icrc_encapsulated_counter[0x1]; 8827 u8 reserved_at_6e[0x4]; 8828 u8 ptys_extended_ethernet[0x1]; 8829 u8 reserved_at_73[0x3]; 8830 u8 pfcc_mask[0x1]; 8831 u8 reserved_at_77[0x3]; 8832 u8 per_lane_error_counters[0x1]; 8833 u8 rx_buffer_fullness_counters[0x1]; 8834 u8 ptys_connector_type[0x1]; 8835 u8 reserved_at_7d[0x1]; 8836 u8 ppcnt_discard_group[0x1]; 8837 u8 ppcnt_statistical_group[0x1]; 8838 }; 8839 8840 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8841 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8842 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8843 8844 u8 reserved_at_40[0xe]; 8845 u8 pddr[0x1]; 8846 u8 reserved_at_4f[0xd]; 8847 8848 u8 pplm[0x1]; 8849 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8850 8851 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8852 u8 pbmc[0x1]; 8853 u8 pptb[0x1]; 8854 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8855 u8 ppcnt[0x1]; 8856 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8857 }; 8858 8859 struct mlx5_ifc_pcam_reg_bits { 8860 u8 reserved_at_0[0x8]; 8861 u8 feature_group[0x8]; 8862 u8 reserved_at_10[0x8]; 8863 u8 access_reg_group[0x8]; 8864 8865 u8 reserved_at_20[0x20]; 8866 8867 union { 8868 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8869 u8 reserved_at_0[0x80]; 8870 } port_access_reg_cap_mask; 8871 8872 u8 reserved_at_c0[0x80]; 8873 8874 union { 8875 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8876 u8 reserved_at_0[0x80]; 8877 } feature_cap_mask; 8878 8879 u8 reserved_at_1c0[0xc0]; 8880 }; 8881 8882 struct mlx5_ifc_mcam_enhanced_features_bits { 8883 u8 reserved_at_0[0x6e]; 8884 u8 pcie_status_and_power[0x1]; 8885 u8 reserved_at_111[0x10]; 8886 u8 pcie_performance_group[0x1]; 8887 }; 8888 8889 struct mlx5_ifc_mcam_access_reg_bits { 8890 u8 reserved_at_0[0x1c]; 8891 u8 mcda[0x1]; 8892 u8 mcc[0x1]; 8893 u8 mcqi[0x1]; 8894 u8 reserved_at_1f[0x1]; 8895 8896 u8 regs_95_to_64[0x20]; 8897 u8 regs_63_to_32[0x20]; 8898 u8 regs_31_to_0[0x20]; 8899 }; 8900 8901 struct mlx5_ifc_mcam_reg_bits { 8902 u8 reserved_at_0[0x8]; 8903 u8 feature_group[0x8]; 8904 u8 reserved_at_10[0x8]; 8905 u8 access_reg_group[0x8]; 8906 8907 u8 reserved_at_20[0x20]; 8908 8909 union { 8910 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8911 u8 reserved_at_0[0x80]; 8912 } mng_access_reg_cap_mask; 8913 8914 u8 reserved_at_c0[0x80]; 8915 8916 union { 8917 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8918 u8 reserved_at_0[0x80]; 8919 } mng_feature_cap_mask; 8920 8921 u8 reserved_at_1c0[0x80]; 8922 }; 8923 8924 struct mlx5_ifc_pcap_reg_bits { 8925 u8 reserved_0[0x8]; 8926 u8 local_port[0x8]; 8927 u8 reserved_1[0x10]; 8928 8929 u8 port_capability_mask[4][0x20]; 8930 }; 8931 8932 struct mlx5_ifc_pbmc_reg_bits { 8933 u8 reserved_at_0[0x8]; 8934 u8 local_port[0x8]; 8935 u8 reserved_at_10[0x10]; 8936 8937 u8 xoff_timer_value[0x10]; 8938 u8 xoff_refresh[0x10]; 8939 8940 u8 reserved_at_40[0x9]; 8941 u8 fullness_threshold[0x7]; 8942 u8 port_buffer_size[0x10]; 8943 8944 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8945 8946 u8 reserved_at_2e0[0x80]; 8947 }; 8948 8949 struct mlx5_ifc_paos_reg_bits { 8950 u8 swid[0x8]; 8951 u8 local_port[0x8]; 8952 u8 reserved_0[0x4]; 8953 u8 admin_status[0x4]; 8954 u8 reserved_1[0x4]; 8955 u8 oper_status[0x4]; 8956 8957 u8 ase[0x1]; 8958 u8 ee[0x1]; 8959 u8 reserved_2[0x1c]; 8960 u8 e[0x2]; 8961 8962 u8 reserved_3[0x40]; 8963 }; 8964 8965 struct mlx5_ifc_pamp_reg_bits { 8966 u8 reserved_0[0x8]; 8967 u8 opamp_group[0x8]; 8968 u8 reserved_1[0xc]; 8969 u8 opamp_group_type[0x4]; 8970 8971 u8 start_index[0x10]; 8972 u8 reserved_2[0x4]; 8973 u8 num_of_indices[0xc]; 8974 8975 u8 index_data[18][0x10]; 8976 }; 8977 8978 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8979 u8 llr_rx_cells_high[0x20]; 8980 8981 u8 llr_rx_cells_low[0x20]; 8982 8983 u8 llr_rx_error_high[0x20]; 8984 8985 u8 llr_rx_error_low[0x20]; 8986 8987 u8 llr_rx_crc_error_high[0x20]; 8988 8989 u8 llr_rx_crc_error_low[0x20]; 8990 8991 u8 llr_tx_cells_high[0x20]; 8992 8993 u8 llr_tx_cells_low[0x20]; 8994 8995 u8 llr_tx_ret_cells_high[0x20]; 8996 8997 u8 llr_tx_ret_cells_low[0x20]; 8998 8999 u8 llr_tx_ret_events_high[0x20]; 9000 9001 u8 llr_tx_ret_events_low[0x20]; 9002 9003 u8 reserved_0[0x640]; 9004 }; 9005 9006 struct mlx5_ifc_mtmp_reg_bits { 9007 u8 i[0x1]; 9008 u8 reserved_at_1[0x18]; 9009 u8 sensor_index[0x7]; 9010 9011 u8 reserved_at_20[0x10]; 9012 u8 temperature[0x10]; 9013 9014 u8 mte[0x1]; 9015 u8 mtr[0x1]; 9016 u8 reserved_at_42[0x0e]; 9017 u8 max_temperature[0x10]; 9018 9019 u8 tee[0x2]; 9020 u8 reserved_at_62[0x0e]; 9021 u8 temperature_threshold_hi[0x10]; 9022 9023 u8 reserved_at_80[0x10]; 9024 u8 temperature_threshold_lo[0x10]; 9025 9026 u8 reserved_at_100[0x20]; 9027 9028 u8 sensor_name[0x40]; 9029 }; 9030 9031 struct mlx5_ifc_lane_2_module_mapping_bits { 9032 u8 reserved_0[0x6]; 9033 u8 rx_lane[0x2]; 9034 u8 reserved_1[0x6]; 9035 u8 tx_lane[0x2]; 9036 u8 reserved_2[0x8]; 9037 u8 module[0x8]; 9038 }; 9039 9040 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 9041 u8 transmit_queue_high[0x20]; 9042 9043 u8 transmit_queue_low[0x20]; 9044 9045 u8 reserved_0[0x780]; 9046 }; 9047 9048 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 9049 u8 no_buffer_discard_uc_high[0x20]; 9050 9051 u8 no_buffer_discard_uc_low[0x20]; 9052 9053 u8 wred_discard_high[0x20]; 9054 9055 u8 wred_discard_low[0x20]; 9056 9057 u8 reserved_0[0x740]; 9058 }; 9059 9060 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 9061 u8 rx_octets_high[0x20]; 9062 9063 u8 rx_octets_low[0x20]; 9064 9065 u8 reserved_0[0xc0]; 9066 9067 u8 rx_frames_high[0x20]; 9068 9069 u8 rx_frames_low[0x20]; 9070 9071 u8 tx_octets_high[0x20]; 9072 9073 u8 tx_octets_low[0x20]; 9074 9075 u8 reserved_1[0xc0]; 9076 9077 u8 tx_frames_high[0x20]; 9078 9079 u8 tx_frames_low[0x20]; 9080 9081 u8 rx_pause_high[0x20]; 9082 9083 u8 rx_pause_low[0x20]; 9084 9085 u8 rx_pause_duration_high[0x20]; 9086 9087 u8 rx_pause_duration_low[0x20]; 9088 9089 u8 tx_pause_high[0x20]; 9090 9091 u8 tx_pause_low[0x20]; 9092 9093 u8 tx_pause_duration_high[0x20]; 9094 9095 u8 tx_pause_duration_low[0x20]; 9096 9097 u8 rx_pause_transition_high[0x20]; 9098 9099 u8 rx_pause_transition_low[0x20]; 9100 9101 u8 rx_discards_high[0x20]; 9102 9103 u8 rx_discards_low[0x20]; 9104 9105 u8 device_stall_minor_watermark_cnt_high[0x20]; 9106 9107 u8 device_stall_minor_watermark_cnt_low[0x20]; 9108 9109 u8 device_stall_critical_watermark_cnt_high[0x20]; 9110 9111 u8 device_stall_critical_watermark_cnt_low[0x20]; 9112 9113 u8 reserved_2[0x340]; 9114 }; 9115 9116 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9117 u8 port_transmit_wait_high[0x20]; 9118 9119 u8 port_transmit_wait_low[0x20]; 9120 9121 u8 ecn_marked_high[0x20]; 9122 9123 u8 ecn_marked_low[0x20]; 9124 9125 u8 no_buffer_discard_mc_high[0x20]; 9126 9127 u8 no_buffer_discard_mc_low[0x20]; 9128 9129 u8 rx_ebp_high[0x20]; 9130 9131 u8 rx_ebp_low[0x20]; 9132 9133 u8 tx_ebp_high[0x20]; 9134 9135 u8 tx_ebp_low[0x20]; 9136 9137 u8 rx_buffer_almost_full_high[0x20]; 9138 9139 u8 rx_buffer_almost_full_low[0x20]; 9140 9141 u8 rx_buffer_full_high[0x20]; 9142 9143 u8 rx_buffer_full_low[0x20]; 9144 9145 u8 rx_icrc_encapsulated_high[0x20]; 9146 9147 u8 rx_icrc_encapsulated_low[0x20]; 9148 9149 u8 reserved_0[0x80]; 9150 9151 u8 tx_stats_pkts64octets_high[0x20]; 9152 9153 u8 tx_stats_pkts64octets_low[0x20]; 9154 9155 u8 tx_stats_pkts65to127octets_high[0x20]; 9156 9157 u8 tx_stats_pkts65to127octets_low[0x20]; 9158 9159 u8 tx_stats_pkts128to255octets_high[0x20]; 9160 9161 u8 tx_stats_pkts128to255octets_low[0x20]; 9162 9163 u8 tx_stats_pkts256to511octets_high[0x20]; 9164 9165 u8 tx_stats_pkts256to511octets_low[0x20]; 9166 9167 u8 tx_stats_pkts512to1023octets_high[0x20]; 9168 9169 u8 tx_stats_pkts512to1023octets_low[0x20]; 9170 9171 u8 tx_stats_pkts1024to1518octets_high[0x20]; 9172 9173 u8 tx_stats_pkts1024to1518octets_low[0x20]; 9174 9175 u8 tx_stats_pkts1519to2047octets_high[0x20]; 9176 9177 u8 tx_stats_pkts1519to2047octets_low[0x20]; 9178 9179 u8 tx_stats_pkts2048to4095octets_high[0x20]; 9180 9181 u8 tx_stats_pkts2048to4095octets_low[0x20]; 9182 9183 u8 tx_stats_pkts4096to8191octets_high[0x20]; 9184 9185 u8 tx_stats_pkts4096to8191octets_low[0x20]; 9186 9187 u8 tx_stats_pkts8192to10239octets_high[0x20]; 9188 9189 u8 tx_stats_pkts8192to10239octets_low[0x20]; 9190 9191 u8 reserved_1[0x2C0]; 9192 }; 9193 9194 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 9195 u8 a_frames_transmitted_ok_high[0x20]; 9196 9197 u8 a_frames_transmitted_ok_low[0x20]; 9198 9199 u8 a_frames_received_ok_high[0x20]; 9200 9201 u8 a_frames_received_ok_low[0x20]; 9202 9203 u8 a_frame_check_sequence_errors_high[0x20]; 9204 9205 u8 a_frame_check_sequence_errors_low[0x20]; 9206 9207 u8 a_alignment_errors_high[0x20]; 9208 9209 u8 a_alignment_errors_low[0x20]; 9210 9211 u8 a_octets_transmitted_ok_high[0x20]; 9212 9213 u8 a_octets_transmitted_ok_low[0x20]; 9214 9215 u8 a_octets_received_ok_high[0x20]; 9216 9217 u8 a_octets_received_ok_low[0x20]; 9218 9219 u8 a_multicast_frames_xmitted_ok_high[0x20]; 9220 9221 u8 a_multicast_frames_xmitted_ok_low[0x20]; 9222 9223 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 9224 9225 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 9226 9227 u8 a_multicast_frames_received_ok_high[0x20]; 9228 9229 u8 a_multicast_frames_received_ok_low[0x20]; 9230 9231 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9232 9233 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9234 9235 u8 a_in_range_length_errors_high[0x20]; 9236 9237 u8 a_in_range_length_errors_low[0x20]; 9238 9239 u8 a_out_of_range_length_field_high[0x20]; 9240 9241 u8 a_out_of_range_length_field_low[0x20]; 9242 9243 u8 a_frame_too_long_errors_high[0x20]; 9244 9245 u8 a_frame_too_long_errors_low[0x20]; 9246 9247 u8 a_symbol_error_during_carrier_high[0x20]; 9248 9249 u8 a_symbol_error_during_carrier_low[0x20]; 9250 9251 u8 a_mac_control_frames_transmitted_high[0x20]; 9252 9253 u8 a_mac_control_frames_transmitted_low[0x20]; 9254 9255 u8 a_mac_control_frames_received_high[0x20]; 9256 9257 u8 a_mac_control_frames_received_low[0x20]; 9258 9259 u8 a_unsupported_opcodes_received_high[0x20]; 9260 9261 u8 a_unsupported_opcodes_received_low[0x20]; 9262 9263 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9264 9265 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9266 9267 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9268 9269 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9270 9271 u8 reserved_0[0x300]; 9272 }; 9273 9274 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9275 u8 dot3stats_alignment_errors_high[0x20]; 9276 9277 u8 dot3stats_alignment_errors_low[0x20]; 9278 9279 u8 dot3stats_fcs_errors_high[0x20]; 9280 9281 u8 dot3stats_fcs_errors_low[0x20]; 9282 9283 u8 dot3stats_single_collision_frames_high[0x20]; 9284 9285 u8 dot3stats_single_collision_frames_low[0x20]; 9286 9287 u8 dot3stats_multiple_collision_frames_high[0x20]; 9288 9289 u8 dot3stats_multiple_collision_frames_low[0x20]; 9290 9291 u8 dot3stats_sqe_test_errors_high[0x20]; 9292 9293 u8 dot3stats_sqe_test_errors_low[0x20]; 9294 9295 u8 dot3stats_deferred_transmissions_high[0x20]; 9296 9297 u8 dot3stats_deferred_transmissions_low[0x20]; 9298 9299 u8 dot3stats_late_collisions_high[0x20]; 9300 9301 u8 dot3stats_late_collisions_low[0x20]; 9302 9303 u8 dot3stats_excessive_collisions_high[0x20]; 9304 9305 u8 dot3stats_excessive_collisions_low[0x20]; 9306 9307 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9308 9309 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9310 9311 u8 dot3stats_carrier_sense_errors_high[0x20]; 9312 9313 u8 dot3stats_carrier_sense_errors_low[0x20]; 9314 9315 u8 dot3stats_frame_too_longs_high[0x20]; 9316 9317 u8 dot3stats_frame_too_longs_low[0x20]; 9318 9319 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9320 9321 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9322 9323 u8 dot3stats_symbol_errors_high[0x20]; 9324 9325 u8 dot3stats_symbol_errors_low[0x20]; 9326 9327 u8 dot3control_in_unknown_opcodes_high[0x20]; 9328 9329 u8 dot3control_in_unknown_opcodes_low[0x20]; 9330 9331 u8 dot3in_pause_frames_high[0x20]; 9332 9333 u8 dot3in_pause_frames_low[0x20]; 9334 9335 u8 dot3out_pause_frames_high[0x20]; 9336 9337 u8 dot3out_pause_frames_low[0x20]; 9338 9339 u8 reserved_0[0x3c0]; 9340 }; 9341 9342 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9343 u8 if_in_octets_high[0x20]; 9344 9345 u8 if_in_octets_low[0x20]; 9346 9347 u8 if_in_ucast_pkts_high[0x20]; 9348 9349 u8 if_in_ucast_pkts_low[0x20]; 9350 9351 u8 if_in_discards_high[0x20]; 9352 9353 u8 if_in_discards_low[0x20]; 9354 9355 u8 if_in_errors_high[0x20]; 9356 9357 u8 if_in_errors_low[0x20]; 9358 9359 u8 if_in_unknown_protos_high[0x20]; 9360 9361 u8 if_in_unknown_protos_low[0x20]; 9362 9363 u8 if_out_octets_high[0x20]; 9364 9365 u8 if_out_octets_low[0x20]; 9366 9367 u8 if_out_ucast_pkts_high[0x20]; 9368 9369 u8 if_out_ucast_pkts_low[0x20]; 9370 9371 u8 if_out_discards_high[0x20]; 9372 9373 u8 if_out_discards_low[0x20]; 9374 9375 u8 if_out_errors_high[0x20]; 9376 9377 u8 if_out_errors_low[0x20]; 9378 9379 u8 if_in_multicast_pkts_high[0x20]; 9380 9381 u8 if_in_multicast_pkts_low[0x20]; 9382 9383 u8 if_in_broadcast_pkts_high[0x20]; 9384 9385 u8 if_in_broadcast_pkts_low[0x20]; 9386 9387 u8 if_out_multicast_pkts_high[0x20]; 9388 9389 u8 if_out_multicast_pkts_low[0x20]; 9390 9391 u8 if_out_broadcast_pkts_high[0x20]; 9392 9393 u8 if_out_broadcast_pkts_low[0x20]; 9394 9395 u8 reserved_0[0x480]; 9396 }; 9397 9398 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9399 u8 ether_stats_drop_events_high[0x20]; 9400 9401 u8 ether_stats_drop_events_low[0x20]; 9402 9403 u8 ether_stats_octets_high[0x20]; 9404 9405 u8 ether_stats_octets_low[0x20]; 9406 9407 u8 ether_stats_pkts_high[0x20]; 9408 9409 u8 ether_stats_pkts_low[0x20]; 9410 9411 u8 ether_stats_broadcast_pkts_high[0x20]; 9412 9413 u8 ether_stats_broadcast_pkts_low[0x20]; 9414 9415 u8 ether_stats_multicast_pkts_high[0x20]; 9416 9417 u8 ether_stats_multicast_pkts_low[0x20]; 9418 9419 u8 ether_stats_crc_align_errors_high[0x20]; 9420 9421 u8 ether_stats_crc_align_errors_low[0x20]; 9422 9423 u8 ether_stats_undersize_pkts_high[0x20]; 9424 9425 u8 ether_stats_undersize_pkts_low[0x20]; 9426 9427 u8 ether_stats_oversize_pkts_high[0x20]; 9428 9429 u8 ether_stats_oversize_pkts_low[0x20]; 9430 9431 u8 ether_stats_fragments_high[0x20]; 9432 9433 u8 ether_stats_fragments_low[0x20]; 9434 9435 u8 ether_stats_jabbers_high[0x20]; 9436 9437 u8 ether_stats_jabbers_low[0x20]; 9438 9439 u8 ether_stats_collisions_high[0x20]; 9440 9441 u8 ether_stats_collisions_low[0x20]; 9442 9443 u8 ether_stats_pkts64octets_high[0x20]; 9444 9445 u8 ether_stats_pkts64octets_low[0x20]; 9446 9447 u8 ether_stats_pkts65to127octets_high[0x20]; 9448 9449 u8 ether_stats_pkts65to127octets_low[0x20]; 9450 9451 u8 ether_stats_pkts128to255octets_high[0x20]; 9452 9453 u8 ether_stats_pkts128to255octets_low[0x20]; 9454 9455 u8 ether_stats_pkts256to511octets_high[0x20]; 9456 9457 u8 ether_stats_pkts256to511octets_low[0x20]; 9458 9459 u8 ether_stats_pkts512to1023octets_high[0x20]; 9460 9461 u8 ether_stats_pkts512to1023octets_low[0x20]; 9462 9463 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9464 9465 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9466 9467 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9468 9469 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9470 9471 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9472 9473 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9474 9475 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9476 9477 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9478 9479 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9480 9481 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9482 9483 u8 reserved_0[0x280]; 9484 }; 9485 9486 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9487 u8 symbol_error_counter[0x10]; 9488 u8 link_error_recovery_counter[0x8]; 9489 u8 link_downed_counter[0x8]; 9490 9491 u8 port_rcv_errors[0x10]; 9492 u8 port_rcv_remote_physical_errors[0x10]; 9493 9494 u8 port_rcv_switch_relay_errors[0x10]; 9495 u8 port_xmit_discards[0x10]; 9496 9497 u8 port_xmit_constraint_errors[0x8]; 9498 u8 port_rcv_constraint_errors[0x8]; 9499 u8 reserved_0[0x8]; 9500 u8 local_link_integrity_errors[0x4]; 9501 u8 excessive_buffer_overrun_errors[0x4]; 9502 9503 u8 reserved_1[0x10]; 9504 u8 vl_15_dropped[0x10]; 9505 9506 u8 port_xmit_data[0x20]; 9507 9508 u8 port_rcv_data[0x20]; 9509 9510 u8 port_xmit_pkts[0x20]; 9511 9512 u8 port_rcv_pkts[0x20]; 9513 9514 u8 port_xmit_wait[0x20]; 9515 9516 u8 reserved_2[0x680]; 9517 }; 9518 9519 struct mlx5_ifc_trc_tlb_reg_bits { 9520 u8 reserved_0[0x80]; 9521 9522 u8 tlb_addr[0][0x40]; 9523 }; 9524 9525 struct mlx5_ifc_trc_read_fifo_reg_bits { 9526 u8 reserved_0[0x10]; 9527 u8 requested_event_num[0x10]; 9528 9529 u8 reserved_1[0x20]; 9530 9531 u8 reserved_2[0x10]; 9532 u8 acual_event_num[0x10]; 9533 9534 u8 reserved_3[0x20]; 9535 9536 u8 event[0][0x40]; 9537 }; 9538 9539 struct mlx5_ifc_trc_lock_reg_bits { 9540 u8 reserved_0[0x1f]; 9541 u8 lock[0x1]; 9542 9543 u8 reserved_1[0x60]; 9544 }; 9545 9546 struct mlx5_ifc_trc_filter_reg_bits { 9547 u8 status[0x1]; 9548 u8 reserved_0[0xf]; 9549 u8 filter_index[0x10]; 9550 9551 u8 reserved_1[0x20]; 9552 9553 u8 filter_val[0x20]; 9554 9555 u8 reserved_2[0x1a0]; 9556 }; 9557 9558 struct mlx5_ifc_trc_event_reg_bits { 9559 u8 status[0x1]; 9560 u8 reserved_0[0xf]; 9561 u8 event_index[0x10]; 9562 9563 u8 reserved_1[0x20]; 9564 9565 u8 event_id[0x20]; 9566 9567 u8 event_selector_val[0x10]; 9568 u8 event_selector_size[0x10]; 9569 9570 u8 reserved_2[0x180]; 9571 }; 9572 9573 struct mlx5_ifc_trc_conf_reg_bits { 9574 u8 limit_en[0x1]; 9575 u8 reserved_0[0x3]; 9576 u8 dump_mode[0x4]; 9577 u8 reserved_1[0x15]; 9578 u8 state[0x3]; 9579 9580 u8 reserved_2[0x20]; 9581 9582 u8 limit_event_index[0x20]; 9583 9584 u8 mkey[0x20]; 9585 9586 u8 fifo_ready_ev_num[0x20]; 9587 9588 u8 reserved_3[0x160]; 9589 }; 9590 9591 struct mlx5_ifc_trc_cap_reg_bits { 9592 u8 reserved_0[0x18]; 9593 u8 dump_mode[0x8]; 9594 9595 u8 reserved_1[0x20]; 9596 9597 u8 num_of_events[0x10]; 9598 u8 num_of_filters[0x10]; 9599 9600 u8 fifo_size[0x20]; 9601 9602 u8 tlb_size[0x10]; 9603 u8 event_size[0x10]; 9604 9605 u8 reserved_2[0x160]; 9606 }; 9607 9608 struct mlx5_ifc_set_node_in_bits { 9609 u8 node_description[64][0x8]; 9610 }; 9611 9612 struct mlx5_ifc_register_power_settings_bits { 9613 u8 reserved_0[0x18]; 9614 u8 power_settings_level[0x8]; 9615 9616 u8 reserved_1[0x60]; 9617 }; 9618 9619 struct mlx5_ifc_register_host_endianess_bits { 9620 u8 he[0x1]; 9621 u8 reserved_0[0x1f]; 9622 9623 u8 reserved_1[0x60]; 9624 }; 9625 9626 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9627 u8 physical_address[0x40]; 9628 }; 9629 9630 struct mlx5_ifc_qtct_reg_bits { 9631 u8 operation_type[0x2]; 9632 u8 cap_local_admin[0x1]; 9633 u8 cap_remote_admin[0x1]; 9634 u8 reserved_0[0x4]; 9635 u8 port_number[0x8]; 9636 u8 reserved_1[0xd]; 9637 u8 prio[0x3]; 9638 9639 u8 reserved_2[0x1d]; 9640 u8 tclass[0x3]; 9641 }; 9642 9643 struct mlx5_ifc_qpdp_reg_bits { 9644 u8 reserved_0[0x8]; 9645 u8 port_number[0x8]; 9646 u8 reserved_1[0x10]; 9647 9648 u8 reserved_2[0x1d]; 9649 u8 pprio[0x3]; 9650 }; 9651 9652 struct mlx5_ifc_port_info_ro_fields_param_bits { 9653 u8 reserved_0[0x8]; 9654 u8 port[0x8]; 9655 u8 max_gid[0x10]; 9656 9657 u8 reserved_1[0x20]; 9658 9659 u8 port_guid[0x40]; 9660 }; 9661 9662 struct mlx5_ifc_nvqc_reg_bits { 9663 u8 type[0x20]; 9664 9665 u8 reserved_0[0x18]; 9666 u8 version[0x4]; 9667 u8 reserved_1[0x2]; 9668 u8 support_wr[0x1]; 9669 u8 support_rd[0x1]; 9670 }; 9671 9672 struct mlx5_ifc_nvia_reg_bits { 9673 u8 reserved_0[0x1d]; 9674 u8 target[0x3]; 9675 9676 u8 reserved_1[0x20]; 9677 }; 9678 9679 struct mlx5_ifc_nvdi_reg_bits { 9680 struct mlx5_ifc_config_item_bits configuration_item_header; 9681 }; 9682 9683 struct mlx5_ifc_nvda_reg_bits { 9684 struct mlx5_ifc_config_item_bits configuration_item_header; 9685 9686 u8 configuration_item_data[0x20]; 9687 }; 9688 9689 struct mlx5_ifc_node_info_ro_fields_param_bits { 9690 u8 system_image_guid[0x40]; 9691 9692 u8 reserved_0[0x40]; 9693 9694 u8 node_guid[0x40]; 9695 9696 u8 reserved_1[0x10]; 9697 u8 max_pkey[0x10]; 9698 9699 u8 reserved_2[0x20]; 9700 }; 9701 9702 struct mlx5_ifc_ets_tcn_config_reg_bits { 9703 u8 g[0x1]; 9704 u8 b[0x1]; 9705 u8 r[0x1]; 9706 u8 reserved_0[0x9]; 9707 u8 group[0x4]; 9708 u8 reserved_1[0x9]; 9709 u8 bw_allocation[0x7]; 9710 9711 u8 reserved_2[0xc]; 9712 u8 max_bw_units[0x4]; 9713 u8 reserved_3[0x8]; 9714 u8 max_bw_value[0x8]; 9715 }; 9716 9717 struct mlx5_ifc_ets_global_config_reg_bits { 9718 u8 reserved_0[0x2]; 9719 u8 r[0x1]; 9720 u8 reserved_1[0x1d]; 9721 9722 u8 reserved_2[0xc]; 9723 u8 max_bw_units[0x4]; 9724 u8 reserved_3[0x8]; 9725 u8 max_bw_value[0x8]; 9726 }; 9727 9728 struct mlx5_ifc_qetc_reg_bits { 9729 u8 reserved_at_0[0x8]; 9730 u8 port_number[0x8]; 9731 u8 reserved_at_10[0x30]; 9732 9733 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9734 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9735 }; 9736 9737 struct mlx5_ifc_nodnic_mac_filters_bits { 9738 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9739 9740 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9741 9742 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9743 9744 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9745 9746 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9747 9748 u8 reserved_0[0xc0]; 9749 }; 9750 9751 struct mlx5_ifc_nodnic_gid_filters_bits { 9752 u8 mgid_filter0[16][0x8]; 9753 9754 u8 mgid_filter1[16][0x8]; 9755 9756 u8 mgid_filter2[16][0x8]; 9757 9758 u8 mgid_filter3[16][0x8]; 9759 }; 9760 9761 enum { 9762 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9763 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9764 }; 9765 9766 enum { 9767 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9768 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9769 }; 9770 9771 struct mlx5_ifc_nodnic_config_reg_bits { 9772 u8 no_dram_nic_revision[0x8]; 9773 u8 hardware_format[0x8]; 9774 u8 support_receive_filter[0x1]; 9775 u8 support_promisc_filter[0x1]; 9776 u8 support_promisc_multicast_filter[0x1]; 9777 u8 reserved_0[0x2]; 9778 u8 log_working_buffer_size[0x3]; 9779 u8 log_pkey_table_size[0x4]; 9780 u8 reserved_1[0x3]; 9781 u8 num_ports[0x1]; 9782 9783 u8 reserved_2[0x2]; 9784 u8 log_max_ring_size[0x6]; 9785 u8 reserved_3[0x18]; 9786 9787 u8 lkey[0x20]; 9788 9789 u8 cqe_format[0x4]; 9790 u8 reserved_4[0x1c]; 9791 9792 u8 node_guid[0x40]; 9793 9794 u8 reserved_5[0x740]; 9795 9796 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9797 9798 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9799 }; 9800 9801 struct mlx5_ifc_vlan_layout_bits { 9802 u8 reserved_0[0x14]; 9803 u8 vlan[0xc]; 9804 9805 u8 reserved_1[0x20]; 9806 }; 9807 9808 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9809 u8 reserved_0[0x20]; 9810 9811 u8 mkey[0x20]; 9812 9813 u8 addressh_63_32[0x20]; 9814 9815 u8 addressl_31_0[0x20]; 9816 }; 9817 9818 struct mlx5_ifc_ud_adrs_vector_bits { 9819 u8 dc_key[0x40]; 9820 9821 u8 ext[0x1]; 9822 u8 reserved_0[0x7]; 9823 u8 destination_qp_dct[0x18]; 9824 9825 u8 static_rate[0x4]; 9826 u8 sl_eth_prio[0x4]; 9827 u8 fl[0x1]; 9828 u8 mlid[0x7]; 9829 u8 rlid_udp_sport[0x10]; 9830 9831 u8 reserved_1[0x20]; 9832 9833 u8 rmac_47_16[0x20]; 9834 9835 u8 rmac_15_0[0x10]; 9836 u8 tclass[0x8]; 9837 u8 hop_limit[0x8]; 9838 9839 u8 reserved_2[0x1]; 9840 u8 grh[0x1]; 9841 u8 reserved_3[0x2]; 9842 u8 src_addr_index[0x8]; 9843 u8 flow_label[0x14]; 9844 9845 u8 rgid_rip[16][0x8]; 9846 }; 9847 9848 struct mlx5_ifc_port_module_event_bits { 9849 u8 reserved_0[0x8]; 9850 u8 module[0x8]; 9851 u8 reserved_1[0xc]; 9852 u8 module_status[0x4]; 9853 9854 u8 reserved_2[0x14]; 9855 u8 error_type[0x4]; 9856 u8 reserved_3[0x8]; 9857 9858 u8 reserved_4[0xa0]; 9859 }; 9860 9861 struct mlx5_ifc_icmd_control_bits { 9862 u8 opcode[0x10]; 9863 u8 status[0x8]; 9864 u8 reserved_0[0x7]; 9865 u8 busy[0x1]; 9866 }; 9867 9868 struct mlx5_ifc_eqe_bits { 9869 u8 reserved_0[0x8]; 9870 u8 event_type[0x8]; 9871 u8 reserved_1[0x8]; 9872 u8 event_sub_type[0x8]; 9873 9874 u8 reserved_2[0xe0]; 9875 9876 union mlx5_ifc_event_auto_bits event_data; 9877 9878 u8 reserved_3[0x10]; 9879 u8 signature[0x8]; 9880 u8 reserved_4[0x7]; 9881 u8 owner[0x1]; 9882 }; 9883 9884 enum { 9885 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9886 }; 9887 9888 struct mlx5_ifc_cmd_queue_entry_bits { 9889 u8 type[0x8]; 9890 u8 reserved_0[0x18]; 9891 9892 u8 input_length[0x20]; 9893 9894 u8 input_mailbox_pointer_63_32[0x20]; 9895 9896 u8 input_mailbox_pointer_31_9[0x17]; 9897 u8 reserved_1[0x9]; 9898 9899 u8 command_input_inline_data[16][0x8]; 9900 9901 u8 command_output_inline_data[16][0x8]; 9902 9903 u8 output_mailbox_pointer_63_32[0x20]; 9904 9905 u8 output_mailbox_pointer_31_9[0x17]; 9906 u8 reserved_2[0x9]; 9907 9908 u8 output_length[0x20]; 9909 9910 u8 token[0x8]; 9911 u8 signature[0x8]; 9912 u8 reserved_3[0x8]; 9913 u8 status[0x7]; 9914 u8 ownership[0x1]; 9915 }; 9916 9917 struct mlx5_ifc_cmd_out_bits { 9918 u8 status[0x8]; 9919 u8 reserved_0[0x18]; 9920 9921 u8 syndrome[0x20]; 9922 9923 u8 command_output[0x20]; 9924 }; 9925 9926 struct mlx5_ifc_cmd_in_bits { 9927 u8 opcode[0x10]; 9928 u8 reserved_0[0x10]; 9929 9930 u8 reserved_1[0x10]; 9931 u8 op_mod[0x10]; 9932 9933 u8 command[0][0x20]; 9934 }; 9935 9936 struct mlx5_ifc_cmd_if_box_bits { 9937 u8 mailbox_data[512][0x8]; 9938 9939 u8 reserved_0[0x180]; 9940 9941 u8 next_pointer_63_32[0x20]; 9942 9943 u8 next_pointer_31_10[0x16]; 9944 u8 reserved_1[0xa]; 9945 9946 u8 block_number[0x20]; 9947 9948 u8 reserved_2[0x8]; 9949 u8 token[0x8]; 9950 u8 ctrl_signature[0x8]; 9951 u8 signature[0x8]; 9952 }; 9953 9954 struct mlx5_ifc_mtt_bits { 9955 u8 ptag_63_32[0x20]; 9956 9957 u8 ptag_31_8[0x18]; 9958 u8 reserved_0[0x6]; 9959 u8 wr_en[0x1]; 9960 u8 rd_en[0x1]; 9961 }; 9962 9963 struct mlx5_ifc_tls_progress_params_bits { 9964 u8 valid[0x1]; 9965 u8 reserved_at_1[0x7]; 9966 u8 pd[0x18]; 9967 9968 u8 next_record_tcp_sn[0x20]; 9969 9970 u8 hw_resync_tcp_sn[0x20]; 9971 9972 u8 record_tracker_state[0x2]; 9973 u8 auth_state[0x2]; 9974 u8 reserved_at_64[0x4]; 9975 u8 hw_offset_record_number[0x18]; 9976 }; 9977 9978 struct mlx5_ifc_tls_static_params_bits { 9979 u8 const_2[0x2]; 9980 u8 tls_version[0x4]; 9981 u8 const_1[0x2]; 9982 u8 reserved_at_8[0x14]; 9983 u8 encryption_standard[0x4]; 9984 9985 u8 reserved_at_20[0x20]; 9986 9987 u8 initial_record_number[0x40]; 9988 9989 u8 resync_tcp_sn[0x20]; 9990 9991 u8 gcm_iv[0x20]; 9992 9993 u8 implicit_iv[0x40]; 9994 9995 u8 reserved_at_100[0x8]; 9996 u8 dek_index[0x18]; 9997 9998 u8 reserved_at_120[0xe0]; 9999 }; 10000 10001 /* Vendor Specific Capabilities, VSC */ 10002 enum { 10003 MLX5_VSC_DOMAIN_ICMD = 0x1, 10004 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 10005 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 10006 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 10007 }; 10008 10009 struct mlx5_ifc_vendor_specific_cap_bits { 10010 u8 type[0x8]; 10011 u8 length[0x8]; 10012 u8 next_pointer[0x8]; 10013 u8 capability_id[0x8]; 10014 10015 u8 status[0x3]; 10016 u8 reserved_0[0xd]; 10017 u8 space[0x10]; 10018 10019 u8 counter[0x20]; 10020 10021 u8 semaphore[0x20]; 10022 10023 u8 flag[0x1]; 10024 u8 reserved_1[0x1]; 10025 u8 address[0x1e]; 10026 10027 u8 data[0x20]; 10028 }; 10029 10030 struct mlx5_ifc_vsc_space_bits { 10031 u8 status[0x3]; 10032 u8 reserved0[0xd]; 10033 u8 space[0x10]; 10034 }; 10035 10036 struct mlx5_ifc_vsc_addr_bits { 10037 u8 flag[0x1]; 10038 u8 reserved0[0x1]; 10039 u8 address[0x1e]; 10040 }; 10041 10042 enum { 10043 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10044 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10045 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10046 }; 10047 10048 enum { 10049 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10050 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10051 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10052 }; 10053 10054 enum { 10055 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 10056 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 10057 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 10058 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 10059 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 10060 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 10061 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 10062 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 10063 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 10064 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 10065 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 10066 }; 10067 10068 struct mlx5_ifc_initial_seg_bits { 10069 u8 fw_rev_minor[0x10]; 10070 u8 fw_rev_major[0x10]; 10071 10072 u8 cmd_interface_rev[0x10]; 10073 u8 fw_rev_subminor[0x10]; 10074 10075 u8 reserved_0[0x40]; 10076 10077 u8 cmdq_phy_addr_63_32[0x20]; 10078 10079 u8 cmdq_phy_addr_31_12[0x14]; 10080 u8 reserved_1[0x2]; 10081 u8 nic_interface[0x2]; 10082 u8 log_cmdq_size[0x4]; 10083 u8 log_cmdq_stride[0x4]; 10084 10085 u8 command_doorbell_vector[0x20]; 10086 10087 u8 reserved_2[0xf00]; 10088 10089 u8 initializing[0x1]; 10090 u8 reserved_3[0x4]; 10091 u8 nic_interface_supported[0x3]; 10092 u8 reserved_4[0x18]; 10093 10094 struct mlx5_ifc_health_buffer_bits health_buffer; 10095 10096 u8 no_dram_nic_offset[0x20]; 10097 10098 u8 reserved_5[0x6de0]; 10099 10100 u8 internal_timer_h[0x20]; 10101 10102 u8 internal_timer_l[0x20]; 10103 10104 u8 reserved_6[0x20]; 10105 10106 u8 reserved_7[0x1f]; 10107 u8 clear_int[0x1]; 10108 10109 u8 health_syndrome[0x8]; 10110 u8 health_counter[0x18]; 10111 10112 u8 reserved_8[0x17fc0]; 10113 }; 10114 10115 union mlx5_ifc_icmd_interface_document_bits { 10116 struct mlx5_ifc_fw_version_bits fw_version; 10117 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10118 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10119 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10120 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10121 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10122 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10123 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10124 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10125 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10126 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10127 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10128 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10129 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10130 u8 reserved_0[0x42c0]; 10131 }; 10132 10133 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 10134 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10135 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10136 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10137 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10138 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10139 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10140 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10141 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10142 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 10143 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 10144 u8 reserved_0[0x7c0]; 10145 }; 10146 10147 struct mlx5_ifc_ppcnt_reg_bits { 10148 u8 swid[0x8]; 10149 u8 local_port[0x8]; 10150 u8 pnat[0x2]; 10151 u8 reserved_0[0x8]; 10152 u8 grp[0x6]; 10153 10154 u8 clr[0x1]; 10155 u8 reserved_1[0x1c]; 10156 u8 prio_tc[0x3]; 10157 10158 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10159 }; 10160 10161 struct mlx5_ifc_pcie_lanes_counters_bits { 10162 u8 life_time_counter_high[0x20]; 10163 10164 u8 life_time_counter_low[0x20]; 10165 10166 u8 error_counter_lane0[0x20]; 10167 10168 u8 error_counter_lane1[0x20]; 10169 10170 u8 error_counter_lane2[0x20]; 10171 10172 u8 error_counter_lane3[0x20]; 10173 10174 u8 error_counter_lane4[0x20]; 10175 10176 u8 error_counter_lane5[0x20]; 10177 10178 u8 error_counter_lane6[0x20]; 10179 10180 u8 error_counter_lane7[0x20]; 10181 10182 u8 error_counter_lane8[0x20]; 10183 10184 u8 error_counter_lane9[0x20]; 10185 10186 u8 error_counter_lane10[0x20]; 10187 10188 u8 error_counter_lane11[0x20]; 10189 10190 u8 error_counter_lane12[0x20]; 10191 10192 u8 error_counter_lane13[0x20]; 10193 10194 u8 error_counter_lane14[0x20]; 10195 10196 u8 error_counter_lane15[0x20]; 10197 10198 u8 reserved_at_240[0x580]; 10199 }; 10200 10201 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 10202 u8 reserved_at_0[0x40]; 10203 10204 u8 error_counter_lane0[0x20]; 10205 10206 u8 error_counter_lane1[0x20]; 10207 10208 u8 error_counter_lane2[0x20]; 10209 10210 u8 error_counter_lane3[0x20]; 10211 10212 u8 error_counter_lane4[0x20]; 10213 10214 u8 error_counter_lane5[0x20]; 10215 10216 u8 error_counter_lane6[0x20]; 10217 10218 u8 error_counter_lane7[0x20]; 10219 10220 u8 error_counter_lane8[0x20]; 10221 10222 u8 error_counter_lane9[0x20]; 10223 10224 u8 error_counter_lane10[0x20]; 10225 10226 u8 error_counter_lane11[0x20]; 10227 10228 u8 error_counter_lane12[0x20]; 10229 10230 u8 error_counter_lane13[0x20]; 10231 10232 u8 error_counter_lane14[0x20]; 10233 10234 u8 error_counter_lane15[0x20]; 10235 10236 u8 reserved_at_240[0x580]; 10237 }; 10238 10239 struct mlx5_ifc_pcie_perf_counters_bits { 10240 u8 life_time_counter_high[0x20]; 10241 10242 u8 life_time_counter_low[0x20]; 10243 10244 u8 rx_errors[0x20]; 10245 10246 u8 tx_errors[0x20]; 10247 10248 u8 l0_to_recovery_eieos[0x20]; 10249 10250 u8 l0_to_recovery_ts[0x20]; 10251 10252 u8 l0_to_recovery_framing[0x20]; 10253 10254 u8 l0_to_recovery_retrain[0x20]; 10255 10256 u8 crc_error_dllp[0x20]; 10257 10258 u8 crc_error_tlp[0x20]; 10259 10260 u8 tx_overflow_buffer_pkt[0x40]; 10261 10262 u8 outbound_stalled_reads[0x20]; 10263 10264 u8 outbound_stalled_writes[0x20]; 10265 10266 u8 outbound_stalled_reads_events[0x20]; 10267 10268 u8 outbound_stalled_writes_events[0x20]; 10269 10270 u8 tx_overflow_buffer_marked_pkt[0x40]; 10271 10272 u8 reserved_at_240[0x580]; 10273 }; 10274 10275 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10276 u8 reserved_at_0[0x40]; 10277 10278 u8 rx_errors[0x20]; 10279 10280 u8 tx_errors[0x20]; 10281 10282 u8 reserved_at_80[0xc0]; 10283 10284 u8 tx_overflow_buffer_pkt[0x40]; 10285 10286 u8 outbound_stalled_reads[0x20]; 10287 10288 u8 outbound_stalled_writes[0x20]; 10289 10290 u8 outbound_stalled_reads_events[0x20]; 10291 10292 u8 outbound_stalled_writes_events[0x20]; 10293 10294 u8 tx_overflow_buffer_marked_pkt[0x40]; 10295 10296 u8 reserved_at_240[0x580]; 10297 }; 10298 10299 struct mlx5_ifc_pcie_timers_states_bits { 10300 u8 life_time_counter_high[0x20]; 10301 10302 u8 life_time_counter_low[0x20]; 10303 10304 u8 time_to_boot_image_start[0x20]; 10305 10306 u8 time_to_link_image[0x20]; 10307 10308 u8 calibration_time[0x20]; 10309 10310 u8 time_to_first_perst[0x20]; 10311 10312 u8 time_to_detect_state[0x20]; 10313 10314 u8 time_to_l0[0x20]; 10315 10316 u8 time_to_crs_en[0x20]; 10317 10318 u8 time_to_plastic_image_start[0x20]; 10319 10320 u8 time_to_iron_image_start[0x20]; 10321 10322 u8 perst_handler[0x20]; 10323 10324 u8 times_in_l1[0x20]; 10325 10326 u8 times_in_l23[0x20]; 10327 10328 u8 dl_down[0x20]; 10329 10330 u8 config_cycle1usec[0x20]; 10331 10332 u8 config_cycle2to7usec[0x20]; 10333 10334 u8 config_cycle8to15usec[0x20]; 10335 10336 u8 config_cycle16to63usec[0x20]; 10337 10338 u8 config_cycle64usec[0x20]; 10339 10340 u8 correctable_err_msg_sent[0x20]; 10341 10342 u8 non_fatal_err_msg_sent[0x20]; 10343 10344 u8 fatal_err_msg_sent[0x20]; 10345 10346 u8 reserved_at_2e0[0x4e0]; 10347 }; 10348 10349 struct mlx5_ifc_pcie_timers_states_ext_bits { 10350 u8 reserved_at_0[0x40]; 10351 10352 u8 time_to_boot_image_start[0x20]; 10353 10354 u8 time_to_link_image[0x20]; 10355 10356 u8 calibration_time[0x20]; 10357 10358 u8 time_to_first_perst[0x20]; 10359 10360 u8 time_to_detect_state[0x20]; 10361 10362 u8 time_to_l0[0x20]; 10363 10364 u8 time_to_crs_en[0x20]; 10365 10366 u8 time_to_plastic_image_start[0x20]; 10367 10368 u8 time_to_iron_image_start[0x20]; 10369 10370 u8 perst_handler[0x20]; 10371 10372 u8 times_in_l1[0x20]; 10373 10374 u8 times_in_l23[0x20]; 10375 10376 u8 dl_down[0x20]; 10377 10378 u8 config_cycle1usec[0x20]; 10379 10380 u8 config_cycle2to7usec[0x20]; 10381 10382 u8 config_cycle8to15usec[0x20]; 10383 10384 u8 config_cycle16to63usec[0x20]; 10385 10386 u8 config_cycle64usec[0x20]; 10387 10388 u8 correctable_err_msg_sent[0x20]; 10389 10390 u8 non_fatal_err_msg_sent[0x20]; 10391 10392 u8 fatal_err_msg_sent[0x20]; 10393 10394 u8 reserved_at_2e0[0x4e0]; 10395 }; 10396 10397 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10398 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10399 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10400 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10401 u8 reserved_at_0[0x7c0]; 10402 }; 10403 10404 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10405 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10406 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10407 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10408 u8 reserved_at_0[0x7c0]; 10409 }; 10410 10411 struct mlx5_ifc_mpcnt_reg_bits { 10412 u8 reserved_at_0[0x2]; 10413 u8 depth[0x6]; 10414 u8 pcie_index[0x8]; 10415 u8 node[0x8]; 10416 u8 reserved_at_18[0x2]; 10417 u8 grp[0x6]; 10418 10419 u8 clr[0x1]; 10420 u8 reserved_at_21[0x1f]; 10421 10422 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10423 }; 10424 10425 struct mlx5_ifc_mpcnt_reg_ext_bits { 10426 u8 reserved_at_0[0x2]; 10427 u8 depth[0x6]; 10428 u8 pcie_index[0x8]; 10429 u8 node[0x8]; 10430 u8 reserved_at_18[0x2]; 10431 u8 grp[0x6]; 10432 10433 u8 clr[0x1]; 10434 u8 reserved_at_21[0x1f]; 10435 10436 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10437 }; 10438 10439 struct mlx5_ifc_monitor_opcodes_layout_bits { 10440 u8 reserved_at_0[0x10]; 10441 u8 monitor_opcode[0x10]; 10442 }; 10443 10444 union mlx5_ifc_pddr_status_opcode_bits { 10445 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 10446 u8 reserved_at_0[0x20]; 10447 }; 10448 10449 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 10450 u8 reserved_at_0[0x10]; 10451 u8 group_opcode[0x10]; 10452 10453 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 10454 10455 u8 user_feedback_data[0x10]; 10456 u8 user_feedback_index[0x10]; 10457 10458 u8 status_message[0x760]; 10459 }; 10460 10461 union mlx5_ifc_pddr_page_data_bits { 10462 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 10463 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 10464 u8 reserved_at_0[0x7c0]; 10465 }; 10466 10467 struct mlx5_ifc_pddr_reg_bits { 10468 u8 reserved_at_0[0x8]; 10469 u8 local_port[0x8]; 10470 u8 pnat[0x2]; 10471 u8 reserved_at_12[0xe]; 10472 10473 u8 reserved_at_20[0x18]; 10474 u8 page_select[0x8]; 10475 10476 union mlx5_ifc_pddr_page_data_bits page_data; 10477 }; 10478 10479 enum { 10480 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10481 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10482 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10483 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10484 }; 10485 10486 struct mlx5_ifc_mpein_reg_bits { 10487 u8 reserved_at_0[0x2]; 10488 u8 depth[0x6]; 10489 u8 pcie_index[0x8]; 10490 u8 node[0x8]; 10491 u8 reserved_at_18[0x8]; 10492 10493 u8 capability_mask[0x20]; 10494 10495 u8 reserved_at_40[0x8]; 10496 u8 link_width_enabled[0x8]; 10497 u8 link_speed_enabled[0x10]; 10498 10499 u8 lane0_physical_position[0x8]; 10500 u8 link_width_active[0x8]; 10501 u8 link_speed_active[0x10]; 10502 10503 u8 num_of_pfs[0x10]; 10504 u8 num_of_vfs[0x10]; 10505 10506 u8 bdf0[0x10]; 10507 u8 reserved_at_b0[0x10]; 10508 10509 u8 max_read_request_size[0x4]; 10510 u8 max_payload_size[0x4]; 10511 u8 reserved_at_c8[0x5]; 10512 u8 pwr_status[0x3]; 10513 u8 port_type[0x4]; 10514 u8 reserved_at_d4[0xb]; 10515 u8 lane_reversal[0x1]; 10516 10517 u8 reserved_at_e0[0x14]; 10518 u8 pci_power[0xc]; 10519 10520 u8 reserved_at_100[0x20]; 10521 10522 u8 device_status[0x10]; 10523 u8 port_state[0x8]; 10524 u8 reserved_at_138[0x8]; 10525 10526 u8 reserved_at_140[0x10]; 10527 u8 receiver_detect_result[0x10]; 10528 10529 u8 reserved_at_160[0x20]; 10530 }; 10531 10532 struct mlx5_ifc_mpein_reg_ext_bits { 10533 u8 reserved_at_0[0x2]; 10534 u8 depth[0x6]; 10535 u8 pcie_index[0x8]; 10536 u8 node[0x8]; 10537 u8 reserved_at_18[0x8]; 10538 10539 u8 reserved_at_20[0x20]; 10540 10541 u8 reserved_at_40[0x8]; 10542 u8 link_width_enabled[0x8]; 10543 u8 link_speed_enabled[0x10]; 10544 10545 u8 lane0_physical_position[0x8]; 10546 u8 link_width_active[0x8]; 10547 u8 link_speed_active[0x10]; 10548 10549 u8 num_of_pfs[0x10]; 10550 u8 num_of_vfs[0x10]; 10551 10552 u8 bdf0[0x10]; 10553 u8 reserved_at_b0[0x10]; 10554 10555 u8 max_read_request_size[0x4]; 10556 u8 max_payload_size[0x4]; 10557 u8 reserved_at_c8[0x5]; 10558 u8 pwr_status[0x3]; 10559 u8 port_type[0x4]; 10560 u8 reserved_at_d4[0xb]; 10561 u8 lane_reversal[0x1]; 10562 }; 10563 10564 struct mlx5_ifc_mcqi_cap_bits { 10565 u8 supported_info_bitmask[0x20]; 10566 10567 u8 component_size[0x20]; 10568 10569 u8 max_component_size[0x20]; 10570 10571 u8 log_mcda_word_size[0x4]; 10572 u8 reserved_at_64[0xc]; 10573 u8 mcda_max_write_size[0x10]; 10574 10575 u8 rd_en[0x1]; 10576 u8 reserved_at_81[0x1]; 10577 u8 match_chip_id[0x1]; 10578 u8 match_psid[0x1]; 10579 u8 check_user_timestamp[0x1]; 10580 u8 match_base_guid_mac[0x1]; 10581 u8 reserved_at_86[0x1a]; 10582 }; 10583 10584 struct mlx5_ifc_mcqi_reg_bits { 10585 u8 read_pending_component[0x1]; 10586 u8 reserved_at_1[0xf]; 10587 u8 component_index[0x10]; 10588 10589 u8 reserved_at_20[0x20]; 10590 10591 u8 reserved_at_40[0x1b]; 10592 u8 info_type[0x5]; 10593 10594 u8 info_size[0x20]; 10595 10596 u8 offset[0x20]; 10597 10598 u8 reserved_at_a0[0x10]; 10599 u8 data_size[0x10]; 10600 10601 u8 data[0][0x20]; 10602 }; 10603 10604 struct mlx5_ifc_mcc_reg_bits { 10605 u8 reserved_at_0[0x4]; 10606 u8 time_elapsed_since_last_cmd[0xc]; 10607 u8 reserved_at_10[0x8]; 10608 u8 instruction[0x8]; 10609 10610 u8 reserved_at_20[0x10]; 10611 u8 component_index[0x10]; 10612 10613 u8 reserved_at_40[0x8]; 10614 u8 update_handle[0x18]; 10615 10616 u8 handle_owner_type[0x4]; 10617 u8 handle_owner_host_id[0x4]; 10618 u8 reserved_at_68[0x1]; 10619 u8 control_progress[0x7]; 10620 u8 error_code[0x8]; 10621 u8 reserved_at_78[0x4]; 10622 u8 control_state[0x4]; 10623 10624 u8 component_size[0x20]; 10625 10626 u8 reserved_at_a0[0x60]; 10627 }; 10628 10629 struct mlx5_ifc_mcda_reg_bits { 10630 u8 reserved_at_0[0x8]; 10631 u8 update_handle[0x18]; 10632 10633 u8 offset[0x20]; 10634 10635 u8 reserved_at_40[0x10]; 10636 u8 size[0x10]; 10637 10638 u8 reserved_at_60[0x20]; 10639 10640 u8 data[0][0x20]; 10641 }; 10642 10643 union mlx5_ifc_ports_control_registers_document_bits { 10644 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10645 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10646 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10647 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10648 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10649 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10650 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10651 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10652 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10653 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10654 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10655 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10656 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10657 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10658 struct mlx5_ifc_paos_reg_bits paos_reg; 10659 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10660 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10661 struct mlx5_ifc_peir_reg_bits peir_reg; 10662 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10663 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10664 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10665 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10666 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10667 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10668 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10669 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10670 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10671 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10672 struct mlx5_ifc_plib_reg_bits plib_reg; 10673 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10674 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10675 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10676 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10677 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10678 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10679 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10680 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10681 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10682 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10683 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10684 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10685 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10686 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10687 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10688 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10689 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10690 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10691 struct mlx5_ifc_pude_reg_bits pude_reg; 10692 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10693 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10694 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10695 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10696 u8 reserved_0[0x7880]; 10697 }; 10698 10699 union mlx5_ifc_debug_enhancements_document_bits { 10700 struct mlx5_ifc_health_buffer_bits health_buffer; 10701 u8 reserved_0[0x200]; 10702 }; 10703 10704 union mlx5_ifc_no_dram_nic_document_bits { 10705 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10706 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10707 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10708 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10709 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10710 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10711 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10712 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10713 u8 reserved_0[0x3160]; 10714 }; 10715 10716 union mlx5_ifc_uplink_pci_interface_document_bits { 10717 struct mlx5_ifc_initial_seg_bits initial_seg; 10718 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10719 u8 reserved_0[0x20120]; 10720 }; 10721 10722 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10723 u8 e[0x1]; 10724 u8 reserved_at_01[0x0b]; 10725 u8 prio[0x04]; 10726 }; 10727 10728 struct mlx5_ifc_qpdpm_reg_bits { 10729 u8 reserved_at_0[0x8]; 10730 u8 local_port[0x8]; 10731 u8 reserved_at_10[0x10]; 10732 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10733 }; 10734 10735 struct mlx5_ifc_qpts_reg_bits { 10736 u8 reserved_at_0[0x8]; 10737 u8 local_port[0x8]; 10738 u8 reserved_at_10[0x2d]; 10739 u8 trust_state[0x3]; 10740 }; 10741 10742 struct mlx5_ifc_mfrl_reg_bits { 10743 u8 reserved_at_0[0x38]; 10744 u8 reset_level[0x8]; 10745 }; 10746 10747 enum { 10748 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 10749 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 10750 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 10751 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 10752 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 10753 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 10754 MLX5_MAX_TEMPERATURE = 16, 10755 }; 10756 10757 struct mlx5_ifc_mtbr_temp_record_bits { 10758 u8 max_temperature[0x10]; 10759 u8 temperature[0x10]; 10760 }; 10761 10762 struct mlx5_ifc_mtbr_reg_bits { 10763 u8 reserved_at_0[0x14]; 10764 u8 base_sensor_index[0xc]; 10765 10766 u8 reserved_at_20[0x18]; 10767 u8 num_rec[0x8]; 10768 10769 u8 reserved_at_40[0x40]; 10770 10771 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10772 }; 10773 10774 struct mlx5_ifc_mtbr_reg_ext_bits { 10775 u8 reserved_at_0[0x14]; 10776 u8 base_sensor_index[0xc]; 10777 10778 u8 reserved_at_20[0x18]; 10779 u8 num_rec[0x8]; 10780 10781 u8 reserved_at_40[0x40]; 10782 10783 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10784 }; 10785 10786 struct mlx5_ifc_mtcap_bits { 10787 u8 reserved_at_0[0x19]; 10788 u8 sensor_count[0x7]; 10789 10790 u8 reserved_at_20[0x19]; 10791 u8 internal_sensor_count[0x7]; 10792 10793 u8 sensor_map[0x40]; 10794 }; 10795 10796 struct mlx5_ifc_mtcap_ext_bits { 10797 u8 reserved_at_0[0x19]; 10798 u8 sensor_count[0x7]; 10799 10800 u8 reserved_at_20[0x20]; 10801 10802 u8 sensor_map[0x40]; 10803 }; 10804 10805 struct mlx5_ifc_mtecr_bits { 10806 u8 reserved_at_0[0x4]; 10807 u8 last_sensor[0xc]; 10808 u8 reserved_at_10[0x4]; 10809 u8 sensor_count[0xc]; 10810 10811 u8 reserved_at_20[0x19]; 10812 u8 internal_sensor_count[0x7]; 10813 10814 u8 sensor_map_0[0x20]; 10815 10816 u8 reserved_at_60[0x2a0]; 10817 }; 10818 10819 struct mlx5_ifc_mtecr_ext_bits { 10820 u8 reserved_at_0[0x4]; 10821 u8 last_sensor[0xc]; 10822 u8 reserved_at_10[0x4]; 10823 u8 sensor_count[0xc]; 10824 10825 u8 reserved_at_20[0x20]; 10826 10827 u8 sensor_map_0[0x20]; 10828 10829 u8 reserved_at_60[0x2a0]; 10830 }; 10831 10832 struct mlx5_ifc_mtewe_bits { 10833 u8 reserved_at_0[0x4]; 10834 u8 last_sensor[0xc]; 10835 u8 reserved_at_10[0x4]; 10836 u8 sensor_count[0xc]; 10837 10838 u8 sensor_warning_0[0x20]; 10839 10840 u8 reserved_at_40[0x2a0]; 10841 }; 10842 10843 struct mlx5_ifc_mtewe_ext_bits { 10844 u8 reserved_at_0[0x4]; 10845 u8 last_sensor[0xc]; 10846 u8 reserved_at_10[0x4]; 10847 u8 sensor_count[0xc]; 10848 10849 u8 sensor_warning_0[0x20]; 10850 10851 u8 reserved_at_40[0x2a0]; 10852 }; 10853 10854 struct mlx5_ifc_mtmp_bits { 10855 u8 reserved_at_0[0x14]; 10856 u8 sensor_index[0xc]; 10857 10858 u8 reserved_at_20[0x10]; 10859 u8 temperature[0x10]; 10860 10861 u8 mte[0x1]; 10862 u8 mtr[0x1]; 10863 u8 reserved_at_42[0xe]; 10864 u8 max_temperature[0x10]; 10865 10866 u8 tee[0x2]; 10867 u8 reserved_at_62[0xe]; 10868 u8 temperature_threshold_hi[0x10]; 10869 10870 u8 reserved_at_80[0x10]; 10871 u8 temperature_threshold_lo[0x10]; 10872 10873 u8 reserved_at_a0[0x20]; 10874 10875 u8 sensor_name_hi[0x20]; 10876 10877 u8 sensor_name_lo[0x20]; 10878 }; 10879 10880 struct mlx5_ifc_mtmp_ext_bits { 10881 u8 reserved_at_0[0x14]; 10882 u8 sensor_index[0xc]; 10883 10884 u8 reserved_at_20[0x10]; 10885 u8 temperature[0x10]; 10886 10887 u8 mte[0x1]; 10888 u8 mtr[0x1]; 10889 u8 reserved_at_42[0xe]; 10890 u8 max_temperature[0x10]; 10891 10892 u8 tee[0x2]; 10893 u8 reserved_at_62[0xe]; 10894 u8 temperature_threshold_hi[0x10]; 10895 10896 u8 reserved_at_80[0x10]; 10897 u8 temperature_threshold_lo[0x10]; 10898 10899 u8 reserved_at_a0[0x20]; 10900 10901 u8 sensor_name_hi[0x20]; 10902 10903 u8 sensor_name_lo[0x20]; 10904 }; 10905 10906 #endif /* MLX5_IFC_H */ 10907