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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAMX.td61 TILE:$src4), []>;
102 let Constraints = "$src4 = $dst" in {
104 GR16:$src2, GR16:$src3, TILE:$src4,
108 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
110 GR16:$src2, GR16:$src3, TILE:$src4,
116 GR16:$src2, GR16:$src3, TILE:$src4,
120 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
122 GR16:$src2, GR16:$src3, TILE:$src4,
161 let Constraints = "$src4 = $dst" in
163 GR16:$src2, GR16:$src3, TILE:$src4,
[all …]
H A DX86InstrXOP.td421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
423 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4),
430 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
433 (i8 timm:$src4))))]>, VEX_W,
436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4),
438 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
441 RC:$src3, (i8 timm:$src4))))]>,
450 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
[all …]
H A DX86InstrAVX512.td11117 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
11125 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
11166 _.RC:$src2, (i8 timm:$src4)),
11175 _.RC:$src2, (i8 timm:$src4)),
11193 _.RC:$src1, (i8 timm:$src4)),
11212 (VPTERNLOG321_imm8 timm:$src4))>;
11220 (VPTERNLOG132_imm8 timm:$src4))>;
11383 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
11390 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
11432 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMapAsm2IntrinV62.gen.td114 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
115 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
117 HvxVR:$src3, imm:$src4),
118 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
122 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
123 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
125 HvxVR:$src3, imm:$src4),
126 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
H A DHexagonIntrinsicsV60.td271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
275 IntRegs:$src3, imm:$src4),
276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
284 HvxVR:$src3, IntRegs:$src4),
285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
293 HvxVR:$src3, IntRegs:$src4),
[all …]
H A DHexagonDepMapAsm2Intrin.td612 def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4),
2419 def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),
2427 def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),
3309 def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3311 def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3313 def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3321 def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
3325 def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
3333 def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3335 def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
[all …]
H A DHexagonIntrinsicsV5.td184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
H A DHexagonIntrinsics.td145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
147 (XformImm u5_0ImmPred:$src4))>;
/freebsd-13.1/sys/contrib/device-tree/src/arm/
H A Dr8a7742-iwg21d-q7.dts183 playback = <&ssi4 &src4 &dvc1>;
H A Dr8a7745-iwg22d-sodimm.dts293 capture = <&ssi4 &src4 &dvc1>;
H A Dr8a7778.dtsi280 src4: src-4 { }; label
659 "sru-src3", "sru-src4", "sru-src5",
H A Dr8a7793.dtsi1072 src4: src-4 { label
H A Dr8a7794.dtsi1053 src4: src-4 { label
H A Dr8a7742.dtsi1025 src4: src-4 { label
H A Dr8a7745.dtsi1217 src4: src-4 { label
H A Dr8a7790.dtsi1206 src4: src-4 { label
H A Dr8a7743.dtsi1285 src4: src-4 { label
H A Dr8a7791.dtsi1325 src4: src-4 { label
/freebsd-13.1/sys/ofed/drivers/infiniband/core/
H A Dib_cma.c3493 struct sockaddr_in *src4, *dst4; in sdp_format_hdr() local
3495 src4 = (struct sockaddr_in *) cma_src_addr(id_priv); in sdp_format_hdr()
3499 sdp_hdr->src_addr.ip4.addr = src4->sin_addr.s_addr; in sdp_format_hdr()
3501 sdp_hdr->port = src4->sin_port; in sdp_format_hdr()
3529 struct sockaddr_in *src4, *dst4; in cma_format_hdr() local
3531 src4 = (struct sockaddr_in *) cma_src_addr(id_priv); in cma_format_hdr()
3535 cma_hdr->src_addr.ip4.addr = src4->sin_addr.s_addr; in cma_format_hdr()
3537 cma_hdr->port = src4->sin_port; in cma_format_hdr()
/freebsd-13.1/sys/contrib/device-tree/Bindings/sound/
H A Drenesas,rsnd.txt51 &src4 &ssi4
443 src4: src-4 {
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td2520 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2524 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2527 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2531 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2534 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2538 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2541 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2545 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
2548 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2552 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td528 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
529 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1290 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1293 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1332 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1335 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
2067 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
2068 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
2087 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
2088 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2385 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2425 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
[all …]
/freebsd-13.1/sys/netinet/
H A Dsctp_output.c5298 struct sockaddr_in *src4; in sctp_are_there_new_addresses() local
5301 src4 = (struct sockaddr_in *)src; in sctp_are_there_new_addresses()
5302 if (sa4->sin_addr.s_addr == src4->sin_addr.s_addr) { in sctp_are_there_new_addresses()
5476 struct sockaddr_in *src4 = (struct sockaddr_in *)src; in sctp_send_initiate_ack() local
5615 stc.address[0] = src4->sin_addr.s_addr; in sctp_send_initiate_ack()
5628 if ((IN4_ISPRIVATE_ADDRESS(&src4->sin_addr)) || in sctp_send_initiate_ack()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DBUFInstructions.td1442 …(ops node:$src0, node:$src1, node:$src2, node:$src3, node:$src4, node:$src5, node:$src6, node:$src…
1443 (vt (Op $src0, $src1, $src2, $src3, $src4, $src5, $src6, $src7)),

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