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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_A2_abs IntRegs:$src1),
15 (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;
16 def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1),
18 def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),
62 def: Pat<(int_hexagon_A2_aslh IntRegs:$src1),
64 def: Pat<(int_hexagon_A2_asrh IntRegs:$src1),
110 def: Pat<(int_hexagon_A2_satb IntRegs:$src1),
112 def: Pat<(int_hexagon_A2_sath IntRegs:$src1),
176 def: Pat<(int_hexagon_A2_tfr IntRegs:$src1),
1811 def: Pat<(int_hexagon_V6_hi HvxWR:$src1),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
13 (MI HvxVR:$src1, IntRegs:$src2)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
28 (MI HvxVR:$src1, HvxVR:$src2)>;
33 (MI HvxWR:$src1, HvxWR:$src2)>;
35 (MI HvxWR:$src1, HvxWR:$src2)>;
92 def: Pat<(IntID IntRegs:$src1),
93 (MI IntRegs:$src1)>;
[all …]
H A DHexagonIntrinsicsV60.td85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
87 (MI IntRegs:$src1)>;
91 def: Pat<(IntID HvxVR:$src1),
92 (MI HvxVR:$src1)>;
95 (MI HvxVR:$src1)>;
99 def: Pat<(IntID HvxWR:$src1),
100 (MI HvxWR:$src1)>;
103 (MI HvxWR:$src1)>;
107 def: Pat<(IntID HvxQR:$src1),
108 (MI HvxQR:$src1)>;
[all …]
H A DHexagonIntrinsics.td135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
136 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
138 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
289 def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
290 (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
294 (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
299 def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
300 (MI HvxVR:$src1, HvxVR:$src1,
305 (MI HvxVR:$src1, HvxVR:$src1, (SUB_128_VAL u3_128_ImmPred:$src2))>,
[all …]
/freebsd-13.1/contrib/sendmail/libsm/
H A Dt-strl.c92 (void) sm_strlcpy(src1[k], "abcdef", sizeof src1);
99 one = sm_strlcpyn(dst1, 10, 3, src1[0], "/", src1[1]);
103 one = sm_strlcpyn(dst1, 5, 3, src1[0], "/", src1[1]);
104 two = sm_snprintf(dst2, 5, "%s/%s", src1[0], src1[1]);
107 one = sm_strlcpyn(dst1, 0, 3, src1[0], "/", src1[1]);
111 one = sm_strlcpyn(dst1, sizeof dst1, 5, src1[0], "/", src1[1], "/", src1[2]);
112 two = sm_snprintf(dst2, sizeof dst2, "%s/%s/%s", src1[0], src1[1], src1[2]);
115 one = sm_strlcpyn(dst1, 15, 5, src1[0], "/", src1[1], "/", src1[2]);
116 two = sm_snprintf(dst2, 15, "%s/%s/%s", src1[0], src1[1], src1[2]);
119 one = sm_strlcpyn(dst1, 20, 5, src1[0], "/", src1[1], "/", src1[2]);
[all …]
H A Db-strcmp.c56 char src1[SIZE], src2[SIZE]; local
87 (void) sm_strlcpy(src1, "1234567890", SIZE);
91 (void) sm_strlcpy(src1, "1234567890", SIZE);
95 (void) sm_strlcpy(src1, "1234567892", SIZE);
100 k, src1, src2);
108 j += strcasecmp(src1, src2);
119 j += sm_strcasecmp(src1, src2);
/freebsd-13.1/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h152 __builtin_ia32_tdpbssd((dst), (src0), (src1))
171 __builtin_ia32_tdpbsud((dst), (src0), (src1))
190 __builtin_ia32_tdpbusd((dst), (src0), (src1))
209 __builtin_ia32_tdpbuud((dst), (src0), (src1))
227 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
361 __tile1024i src1) { in __tile_dpbssd() argument
363 src0.tile, src1.tile); in __tile_dpbssd()
384 __tile1024i src1) { in __tile_dpbsud() argument
407 __tile1024i src1) { in __tile_dpbusd() argument
430 __tile1024i src1) { in __tile_dpbuud() argument
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrXOP.td174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
251 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
259 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrShiftRotate.td522 "rol{b}\t{$src1, $dst|$dst, $src1}",
525 "rol{w}\t{$src1, $dst|$dst, $src1}",
529 "rol{l}\t{$src1, $dst|$dst, $src1}",
533 "rol{q}\t{$src1, $dst|$dst, $src1}",
812 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>;
813 def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>;
814 def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>;
815 def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>;
816 def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>;
817 def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>;
[all …]
H A DX86InstrKL.td21 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
22 "loadiwkey\t{$src2, $src1|$src1, $src2}",
39 let Constraints = "$src1 = $dst",
42 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
44 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
48 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
50 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
54 "aesenc256kl\t{$src2, $src1|$src1, $src2}",
56 (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8XS,
60 "aesdec256kl\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrSSE.td5627 "vptest\t{$src2, $src1|$src1, $src2}",
5631 "vptest\t{$src2, $src1|$src1, $src2}",
5637 "vptest\t{$src2, $src1|$src1, $src2}",
5641 "vptest\t{$src2, $src1|$src1, $src2}",
5649 "ptest\t{$src2, $src1|$src1, $src2}",
5653 "ptest\t{$src2, $src1|$src1, $src2}",
6592 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
6764 "vaesimc\t{$src1, $dst|$dst, $src1}",
6770 "vaesimc\t{$src1, $dst|$dst, $src1}",
6776 "aesimc\t{$src1, $dst|$dst, $src1}",
[all …]
H A DX86InstrAMX.td59 def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
71 def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
82 let Constraints = "$src1 = $dst" in {
132 def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1,
134 [(int_x86_tdpbssd timm:$src1,
136 def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1,
138 [(int_x86_tdpbsud timm:$src1,
140 def PTDPBUSD : PseudoI<(outs), (ins u8imm:$src1,
144 def PTDPBUUD : PseudoI<(outs), (ins u8imm:$src1,
154 let Constraints = "$src1 = $dst" in
[all …]
H A DX86InstrArithmetic.td203 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
209 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
241 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
254 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
645 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
695 mnemonic, "{$src2, $src1|$src1, $src2}", []>,
708 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
717 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
751 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
[all …]
H A DX86InstrFMA.td397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
404 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
411 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
436 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
442 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
474 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
481 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
488 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
501 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
508 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrCompiler.td1281 (TEST8rr GR8:$src1, GR8:$src1)>;
1283 (TEST16rr GR16:$src1, GR16:$src1)>;
1285 (TEST32rr GR32:$src1, GR32:$src1)>;
1287 (TEST64rr GR64:$src1, GR64:$src1)>;
1760 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1761 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1762 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1763 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2102 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
2103 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
[all …]
H A DX86InstrAVX512.td301 // $src1.
828 "$idx, $src1", "$src1, $idx",
4585 "$src2, $src1", "$src1, $src2",
5444 "$src2, $src1", "$src1, $src2",
5584 "$src2, $src1", "$src1, $src2",
5589 "$src2, $src1", "$src1, $src2",
9932 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
9994 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
9999 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
10595 "$src1", "$src1",
[all …]
H A DX86InstrCMovSetCC.td17 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
35 (X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
38 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
43 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
48 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
53 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
55 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
67 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
[all …]
H A DX86InstrMPX.td30 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
31 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
33 def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
34 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
37 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
38 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
40 def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
41 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
H A DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
27 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
28 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
30 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
H A DX86InstrMMX.td32 let Constraints = "$src1 = $dst" in {
38 (ins VR64:$src1, VR64:$src2),
45 (ins VR64:$src1, OType:$src2),
94 (ins VR64:$src1, VR64:$src2),
99 (ins VR64:$src1, i64mem:$src2),
375 let Constraints = "$src1 = $dst" in
478 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
484 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
507 let Constraints = "$src1 = $dst" in {
518 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td188 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
191 // out = (src1 > src0) ? 1 : 0
228 // src1 = Denominator, src2 = Numerator).
253 // src1: dst - rat offset (aka pointer) in dwords
322 SDTCisSameAs<3, 2>, // f32 src1
387 [(int_amdgcn_ldexp node:$src0, node:$src1),
388 (AMDGPUldexp_impl node:$src0, node:$src1)]>;
391 [(int_amdgcn_class node:$src0, node:$src1),
392 (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
439 [(int_amdgcn_mul_u24 node:$src0, node:$src1),
[all …]
/freebsd-13.1/contrib/cortex-strings/src/arm/
H A Dstrcmp.S81 #define src1 r0 macro
164 ldrb r2, [src1]
176 orr tmp1, src1, src2
185 eor tmp1, src1, src2
191 and tmp1, src1, #7
192 bic src1, src1, #7
254 ands tmp1, src1, #3
260 ldr data1, [src1], #8
283 bic src1, src1, #3
296 ands tmp1, src1, #3
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DGenericOpcodes.td869 let InOperandList = (ins type0:$src1);
876 let InOperandList = (ins type0:$src1);
883 let InOperandList = (ins type0:$src1);
890 let InOperandList = (ins type0:$src1);
897 let InOperandList = (ins type0:$src1);
904 let InOperandList = (ins type0:$src1);
911 let InOperandList = (ins type0:$src1);
918 let InOperandList = (ins type0:$src1);
928 let InOperandList = (ins type0:$src1);
935 let InOperandList = (ins type0:$src1);
[all …]
/freebsd-13.1/contrib/cortex-strings/src/aarch64/
H A Dmemcmp.S43 #define src1 x0 macro
65 eor tmp1, src1, src2
68 ands tmp1, src1, #7
74 ldr data1, [src1], #8
125 bic src1, src1, #7
129 ldr data1, [src1], #8
155 ldrb data1w, [src1], #1
H A Dstrcmp.S45 #define src1 x0 macro
65 eor tmp1, src1, src2
69 ands tmp1, src1, #7
75 ldr data1, [src1], #8
140 bic src1, src1, #7
143 ldr data1, [src1], #8
160 ldrb data1w, [src1], #1

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