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Searched refs:regclass (Results 1 – 14 of 14) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td2431 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2437 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2443 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2449 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2455 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2520 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2527 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2534 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2541 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2548 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
[all …]
H A DNVPTXIntrinsics.td1262 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b, regclass:$c))]>,
1947 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1950 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1953 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1956 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1959 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2068 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2071 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2074 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2077 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
[all …]
/freebsd-13.1/contrib/llvm-project/libunwind/src/
H A DUnwind-EHABI.cpp762 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Set() argument
767 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Set()
771 switch (regclass) { in _Unwind_VRS_Set()
821 _Unwind_VRS_RegClass regclass, uint32_t regno, in _Unwind_VRS_Get_Internal() argument
825 switch (regclass) { in _Unwind_VRS_Get_Internal()
874 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Get() argument
878 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, in _Unwind_VRS_Get()
882 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Get()
896 switch (regclass) { in _Unwind_VRS_Pop()
916 if (regclass == _UVRSC_CORE && i == 13) in _Unwind_VRS_Pop()
[all …]
/freebsd-13.1/contrib/llvm-project/libunwind/include/
H A Dunwind.h204 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
209 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
214 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
/freebsd-13.1/contrib/libcxxrt/
H A Dunwind-arm.h132 _Unwind_VRS_RegClass regclass,
137 _Unwind_VRS_RegClass regclass,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrCDE.td471 class CDE_VCX_RegisterOperandsTemplate<RegisterClass regclass>
473 let Rd = (outs regclass:$Vd);
474 let Rd_src = (ins regclass:$Vd_src);
475 let Rn = (ins regclass:$Vn);
476 let Rm = (ins regclass:$Vm);
479 class CDE_VCXQ_RegisterOperandsTemplate<RegisterClass regclass>
481 let Rd = (outs regclass:$Qd);
482 let Rd_src = (ins regclass:$Qd_src);
483 let Rn = (ins regclass:$Qn);
484 let Rm = (ins regclass:$Qm);
H A DARMInstrThumb2.td1504 // can be SP. We need another regclass (similar to rGPR) to represent
H A DARMInstrInfo.td2529 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td732 /// type that it doesn't know, and resolves the actual regclass to use by using
845 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
848 RegisterClass RegClass = regclass;
1105 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td539 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
554 RegisterClass RegClass = regclass;
657 // both a regclass and EFLAGS as a result.
665 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def101 // pair. Once it has been lowered to a MachineInstr, the regclass operand
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td48 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
51 VReg vrclass = regclass;
91 class FPR_Info<RegisterClass regclass, string fx> {
92 RegisterClass fprclass = regclass;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td248 // Condition code regclass.
H A DAArch64InstrFormats.td984 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
988 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
1014 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
1018 let MIOperandInfo = (ops regclass, shiftop);