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Searched refs:regVal (Results 1 – 5 of 5) sorted by relevance

/freebsd-13.1/sys/dev/ath/ath_hal/ar9002/
H A Dar9285_diversity.c66 int regVal; in ar9285SetAntennaSwitch() local
88 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9285SetAntennaSwitch()
89 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); in ar9285SetAntennaSwitch()
123 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); in ar9285SetAntennaSwitch()
124 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9285SetAntennaSwitch()
125 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); in ar9285SetAntennaSwitch()
126 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); in ar9285SetAntennaSwitch()
130 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); in ar9285SetAntennaSwitch()
131 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); in ar9285SetAntennaSwitch()
152 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS)); in ar9285SetAntennaSwitch()
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H A Dar9285_btcoex.c49 u_int32_t regVal; in ar9285BTCoexAntennaDiversity() local
107 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9285BTCoexAntennaDiversity()
108 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); in ar9285BTCoexAntennaDiversity()
113 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS)); in ar9285BTCoexAntennaDiversity()
115 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); in ar9285BTCoexAntennaDiversity()
116 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285BTCoexAntennaDiversity()
120 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); in ar9285BTCoexAntennaDiversity()
122 regVal = OS_REG_READ(ah, AR_PHY_CCK_DETECT); in ar9285BTCoexAntennaDiversity()
123 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); in ar9285BTCoexAntennaDiversity()
124 regVal |= SM((ant_div_control1 >> 3), in ar9285BTCoexAntennaDiversity()
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H A Dar9285_cal.c53 uint32_t regVal; in ar9285_hw_pa_cal() local
76 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
77 regVal &= (~(0x1)); in ar9285_hw_pa_cal()
78 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
79 regVal = OS_REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
80 regVal |= (0x1 << 27); in ar9285_hw_pa_cal()
81 OS_REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
105 regVal |= (1 << (19 + i)); in ar9285_hw_pa_cal()
109 regVal &= (~(0x1 << (19 + i))); in ar9285_hw_pa_cal()
142 regVal |= 0x1; in ar9285_hw_pa_cal()
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/freebsd-13.1/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsahw.c574 bit32 regVal; in siChipResetV() local
596 regVal = 1; in siChipResetV()
644 if(regVal == 0xFFFFFFFF) in siChipResetV()
839 bit32 regVal; in siChipResetSpc() local
1054 regVal &= ~(0x00003b00); in siSpcSoftReset()
1107 regVal &= 0xFFFFFFFC; in siSpcSoftReset()
1338 bit32 regVal; in siBar4Shift() local
1595 regVal ++; in siHDAMode()
1596 regVal = (HDA_C_PA << SHIFT24) | (regVal << SHIFT16) | HDAC_EXEC_CMD; in siHDAMode()
1612 if ((HDAR_EXEC == regVal) || (HDAR_BAD_IMG == regVal) || (HDAR_BAD_CMD == regVal)) in siHDAMode()
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/freebsd-13.1/contrib/sqlite3/
H A Dsqlite3.c158456 int regVal, /* Register containing non-negative number */
158487 reg1, (arith==OP_Add ? "+" : "-"), regVal,
158556 sqlite3VdbeAddOp3(v, arith, regVal, reg1, reg1);