1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2015 Nahanni Systems, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/types.h>
35 #include <sys/mman.h>
36
37 #include <machine/vmm.h>
38 #include <machine/vmm_snapshot.h>
39 #include <vmmapi.h>
40
41 #include <stdio.h>
42 #include <stdlib.h>
43 #include <string.h>
44
45 #include <errno.h>
46 #include <unistd.h>
47
48 #include "bhyvegc.h"
49 #include "bhyverun.h"
50 #include "config.h"
51 #include "debug.h"
52 #include "console.h"
53 #include "inout.h"
54 #include "pci_emul.h"
55 #include "rfb.h"
56 #include "vga.h"
57
58 /*
59 * bhyve Framebuffer device emulation.
60 * BAR0 points to the current mode information.
61 * BAR1 is the 32-bit framebuffer address.
62 *
63 * -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
64 */
65
66 static int fbuf_debug = 1;
67 #define DEBUG_INFO 1
68 #define DEBUG_VERBOSE 4
69 #define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params
70
71
72 #define KB (1024UL)
73 #define MB (1024 * 1024UL)
74
75 #define DMEMSZ 128
76
77 #define FB_SIZE (16*MB)
78
79 #define COLS_MAX 1920
80 #define ROWS_MAX 1200
81
82 #define COLS_DEFAULT 1024
83 #define ROWS_DEFAULT 768
84
85 #define COLS_MIN 640
86 #define ROWS_MIN 480
87
88 struct pci_fbuf_softc {
89 struct pci_devinst *fsc_pi;
90 struct {
91 uint32_t fbsize;
92 uint16_t width;
93 uint16_t height;
94 uint16_t depth;
95 uint16_t refreshrate;
96 uint8_t reserved[116];
97 } __packed memregs;
98
99 /* rfb server */
100 char *rfb_host;
101 char *rfb_password;
102 int rfb_port;
103 int rfb_wait;
104 int vga_enabled;
105 int vga_full;
106
107 uint32_t fbaddr;
108 char *fb_base;
109 uint16_t gc_width;
110 uint16_t gc_height;
111 void *vgasc;
112 struct bhyvegc_image *gc_image;
113 };
114
115 static struct pci_fbuf_softc *fbuf_sc;
116
117 #define PCI_FBUF_MSI_MSGS 4
118
119 static void
pci_fbuf_write(struct vmctx * ctx,int vcpu,struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)120 pci_fbuf_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
121 int baridx, uint64_t offset, int size, uint64_t value)
122 {
123 struct pci_fbuf_softc *sc;
124 uint8_t *p;
125
126 assert(baridx == 0);
127
128 sc = pi->pi_arg;
129
130 DPRINTF(DEBUG_VERBOSE,
131 ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx",
132 offset, size, value));
133
134 if (offset + size > DMEMSZ) {
135 printf("fbuf: write too large, offset %ld size %d\n",
136 offset, size);
137 return;
138 }
139
140 p = (uint8_t *)&sc->memregs + offset;
141
142 switch (size) {
143 case 1:
144 *p = value;
145 break;
146 case 2:
147 *(uint16_t *)p = value;
148 break;
149 case 4:
150 *(uint32_t *)p = value;
151 break;
152 case 8:
153 *(uint64_t *)p = value;
154 break;
155 default:
156 printf("fbuf: write unknown size %d\n", size);
157 break;
158 }
159
160 if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
161 sc->memregs.height == 0) {
162 DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
163 sc->gc_image->vgamode = 1;
164 sc->gc_width = 0;
165 sc->gc_height = 0;
166 } else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
167 sc->memregs.height != 0) {
168 DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
169 sc->gc_image->vgamode = 0;
170 }
171 }
172
173 uint64_t
pci_fbuf_read(struct vmctx * ctx,int vcpu,struct pci_devinst * pi,int baridx,uint64_t offset,int size)174 pci_fbuf_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
175 int baridx, uint64_t offset, int size)
176 {
177 struct pci_fbuf_softc *sc;
178 uint8_t *p;
179 uint64_t value;
180
181 assert(baridx == 0);
182
183 sc = pi->pi_arg;
184
185
186 if (offset + size > DMEMSZ) {
187 printf("fbuf: read too large, offset %ld size %d\n",
188 offset, size);
189 return (0);
190 }
191
192 p = (uint8_t *)&sc->memregs + offset;
193 value = 0;
194 switch (size) {
195 case 1:
196 value = *p;
197 break;
198 case 2:
199 value = *(uint16_t *)p;
200 break;
201 case 4:
202 value = *(uint32_t *)p;
203 break;
204 case 8:
205 value = *(uint64_t *)p;
206 break;
207 default:
208 printf("fbuf: read unknown size %d\n", size);
209 break;
210 }
211
212 DPRINTF(DEBUG_VERBOSE,
213 ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx",
214 offset, size, value));
215
216 return (value);
217 }
218
219 static void
pci_fbuf_baraddr(struct vmctx * ctx,struct pci_devinst * pi,int baridx,int enabled,uint64_t address)220 pci_fbuf_baraddr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
221 int enabled, uint64_t address)
222 {
223 struct pci_fbuf_softc *sc;
224 int prot;
225
226 if (baridx != 1)
227 return;
228
229 sc = pi->pi_arg;
230 if (!enabled) {
231 if (vm_munmap_memseg(ctx, sc->fbaddr, FB_SIZE) != 0)
232 EPRINTLN("pci_fbuf: munmap_memseg failed");
233 sc->fbaddr = 0;
234 } else {
235 prot = PROT_READ | PROT_WRITE;
236 if (vm_mmap_memseg(ctx, address, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0)
237 EPRINTLN("pci_fbuf: mmap_memseg failed");
238 sc->fbaddr = address;
239 }
240 }
241
242
243 static int
pci_fbuf_parse_config(struct pci_fbuf_softc * sc,nvlist_t * nvl)244 pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl)
245 {
246 const char *value;
247 char *cp;
248
249 sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false);
250
251 /* Prefer "rfb" to "tcp". */
252 value = get_config_value_node(nvl, "rfb");
253 if (value == NULL)
254 value = get_config_value_node(nvl, "tcp");
255 if (value != NULL) {
256 /*
257 * IPv4 -- host-ip:port
258 * IPv6 -- [host-ip%zone]:port
259 * XXX for now port is mandatory for IPv4.
260 */
261 if (value[0] == '[') {
262 cp = strchr(value + 1, ']');
263 if (cp == NULL || cp == value + 1) {
264 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
265 value);
266 return (-1);
267 }
268 sc->rfb_host = strndup(value + 1, cp - (value + 1));
269 cp++;
270 if (*cp == ':') {
271 cp++;
272 if (*cp == '\0') {
273 EPRINTLN(
274 "fbuf: Missing port number: \"%s\"",
275 value);
276 return (-1);
277 }
278 sc->rfb_port = atoi(cp);
279 } else if (*cp != '\0') {
280 EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
281 value);
282 return (-1);
283 }
284 } else {
285 cp = strchr(value, ':');
286 if (cp == NULL) {
287 sc->rfb_port = atoi(value);
288 } else {
289 sc->rfb_host = strndup(value, cp - value);
290 cp++;
291 if (*cp == '\0') {
292 EPRINTLN(
293 "fbuf: Missing port number: \"%s\"",
294 value);
295 return (-1);
296 }
297 sc->rfb_port = atoi(cp);
298 }
299 }
300 }
301
302 value = get_config_value_node(nvl, "vga");
303 if (value != NULL) {
304 if (strcmp(value, "off") == 0) {
305 sc->vga_enabled = 0;
306 } else if (strcmp(value, "io") == 0) {
307 sc->vga_enabled = 1;
308 sc->vga_full = 0;
309 } else if (strcmp(value, "on") == 0) {
310 sc->vga_enabled = 1;
311 sc->vga_full = 1;
312 } else {
313 EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value);
314 return (-1);
315 }
316 }
317
318 value = get_config_value_node(nvl, "w");
319 if (value != NULL) {
320 sc->memregs.width = atoi(value);
321 if (sc->memregs.width > COLS_MAX) {
322 EPRINTLN("fbuf: width %d too large", sc->memregs.width);
323 return (-1);
324 }
325 if (sc->memregs.width == 0)
326 sc->memregs.width = 1920;
327 }
328
329 value = get_config_value_node(nvl, "h");
330 if (value != NULL) {
331 sc->memregs.height = atoi(value);
332 if (sc->memregs.height > ROWS_MAX) {
333 EPRINTLN("fbuf: height %d too large",
334 sc->memregs.height);
335 return (-1);
336 }
337 if (sc->memregs.height == 0)
338 sc->memregs.height = 1080;
339 }
340
341 value = get_config_value_node(nvl, "password");
342 if (value != NULL)
343 sc->rfb_password = strdup(value);
344
345 return (0);
346 }
347
348
349 extern void vga_render(struct bhyvegc *gc, void *arg);
350
351 void
pci_fbuf_render(struct bhyvegc * gc,void * arg)352 pci_fbuf_render(struct bhyvegc *gc, void *arg)
353 {
354 struct pci_fbuf_softc *sc;
355
356 sc = arg;
357
358 if (sc->vga_full && sc->gc_image->vgamode) {
359 /* TODO: mode switching to vga and vesa should use the special
360 * EFI-bhyve protocol port.
361 */
362 vga_render(gc, sc->vgasc);
363 return;
364 }
365 if (sc->gc_width != sc->memregs.width ||
366 sc->gc_height != sc->memregs.height) {
367 bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
368 sc->gc_width = sc->memregs.width;
369 sc->gc_height = sc->memregs.height;
370 }
371
372 return;
373 }
374
375 static int
pci_fbuf_init(struct vmctx * ctx,struct pci_devinst * pi,nvlist_t * nvl)376 pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
377 {
378 int error;
379 struct pci_fbuf_softc *sc;
380
381 if (fbuf_sc != NULL) {
382 EPRINTLN("Only one frame buffer device is allowed.");
383 return (-1);
384 }
385
386 sc = calloc(1, sizeof(struct pci_fbuf_softc));
387
388 pi->pi_arg = sc;
389
390 /* initialize config space */
391 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
392 pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
393 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
394 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
395
396 sc->fb_base = vm_create_devmem(
397 ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE);
398 if (sc->fb_base == MAP_FAILED) {
399 error = -1;
400 goto done;
401 }
402
403 error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
404 assert(error == 0);
405
406 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
407 assert(error == 0);
408
409 error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
410 assert(error == 0);
411
412 sc->memregs.fbsize = FB_SIZE;
413 sc->memregs.width = COLS_DEFAULT;
414 sc->memregs.height = ROWS_DEFAULT;
415 sc->memregs.depth = 32;
416
417 sc->vga_enabled = 1;
418 sc->vga_full = 0;
419
420 sc->fsc_pi = pi;
421
422 error = pci_fbuf_parse_config(sc, nvl);
423 if (error != 0)
424 goto done;
425
426 /* XXX until VGA rendering is enabled */
427 if (sc->vga_full != 0) {
428 EPRINTLN("pci_fbuf: VGA rendering not enabled");
429 goto done;
430 }
431
432 DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
433 sc->fb_base, FB_SIZE));
434
435 console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
436 console_fb_register(pci_fbuf_render, sc);
437
438 if (sc->vga_enabled)
439 sc->vgasc = vga_init(!sc->vga_full);
440 sc->gc_image = console_get_image();
441
442 fbuf_sc = sc;
443
444 memset((void *)sc->fb_base, 0, FB_SIZE);
445
446 error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
447 done:
448 if (error)
449 free(sc);
450
451 return (error);
452 }
453
454 #ifdef BHYVE_SNAPSHOT
455 static int
pci_fbuf_snapshot(struct vm_snapshot_meta * meta)456 pci_fbuf_snapshot(struct vm_snapshot_meta *meta)
457 {
458 int ret;
459
460 SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err);
461
462 err:
463 return (ret);
464 }
465 #endif
466
467 struct pci_devemu pci_fbuf = {
468 .pe_emu = "fbuf",
469 .pe_init = pci_fbuf_init,
470 .pe_barwrite = pci_fbuf_write,
471 .pe_barread = pci_fbuf_read,
472 .pe_baraddr = pci_fbuf_baraddr,
473 #ifdef BHYVE_SNAPSHOT
474 .pe_snapshot = pci_fbuf_snapshot,
475 #endif
476 };
477 PCI_EMUL_SET(pci_fbuf);
478