| /freebsd-13.1/sys/dev/qat/ |
| H A D | qat_c62x.c | 175 qat_misc_write_4(sc, SMIAPF0_C62X, SMIA0_MASK_C62X); in qat_c62x_enable_intr() 176 qat_misc_write_4(sc, SMIAPF1_C62X, SMIA1_MASK_C62X); in qat_c62x_enable_intr() 200 qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_C62X); /* ME0-ME3 */ in qat_c62x_enable_error_interrupts() 201 qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_C62X); /* ME4-ME7 */ in qat_c62x_enable_error_interrupts() 202 qat_misc_write_4(sc, ERRMSK4, ERRMSK4_CERR_C62X); /* ME8-ME9 */ in qat_c62x_enable_error_interrupts() 211 qat_misc_write_4(sc, RICPPINTCTL_C62X, RICPP_EN_C62X); in qat_c62x_enable_error_interrupts() 214 qat_misc_write_4(sc, TICPPINTCTL_C62X, TICPP_EN_C62X); in qat_c62x_enable_error_interrupts() 217 qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_C62X, CPP_CFC_UE_C62X); in qat_c62x_enable_error_interrupts() 220 qat_misc_write_4(sc, SECRAMCERR_C62X, SECRAM_CERR_C62X); in qat_c62x_enable_error_interrupts() 223 qat_misc_write_4(sc, SECRAMUERR, SECRAM_UERR_C62X); in qat_c62x_enable_error_interrupts() [all …]
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| H A D | qat_d15xx.c | 175 qat_misc_write_4(sc, SMIAPF0_D15XX, SMIA0_MASK_D15XX); in qat_d15xx_enable_intr() 176 qat_misc_write_4(sc, SMIAPF1_D15XX, SMIA1_MASK_D15XX); in qat_d15xx_enable_intr() 200 qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_D15XX); /* ME0-ME3 */ in qat_d15xx_enable_error_interrupts() 201 qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_D15XX); /* ME4-ME7 */ in qat_d15xx_enable_error_interrupts() 202 qat_misc_write_4(sc, ERRMSK4, ERRMSK4_CERR_D15XX); /* ME8-ME9 */ in qat_d15xx_enable_error_interrupts() 211 qat_misc_write_4(sc, RICPPINTCTL_D15XX, RICPP_EN_D15XX); in qat_d15xx_enable_error_interrupts() 214 qat_misc_write_4(sc, TICPPINTCTL_D15XX, TICPP_EN_D15XX); in qat_d15xx_enable_error_interrupts() 217 qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_D15XX, CPP_CFC_UE_D15XX); in qat_d15xx_enable_error_interrupts() 220 qat_misc_write_4(sc, SECRAMCERR_D15XX, SECRAM_CERR_D15XX); in qat_d15xx_enable_error_interrupts() 223 qat_misc_write_4(sc, SECRAMUERR, SECRAM_UERR_D15XX); in qat_d15xx_enable_error_interrupts() [all …]
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| H A D | qat_c3xxx.c | 173 qat_misc_write_4(sc, SMIAPF0_C3XXX, SMIA0_MASK_C3XXX); in qat_c3xxx_enable_intr() 174 qat_misc_write_4(sc, SMIAPF1_C3XXX, SMIA1_MASK_C3XXX); in qat_c3xxx_enable_intr() 198 qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_C3XXX); /* ME0-ME3 */ in qat_c3xxx_enable_error_interrupts() 199 qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_C3XXX); /* ME4-ME5 */ in qat_c3xxx_enable_error_interrupts() 200 qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_C3XXX); /* SSM2 */ in qat_c3xxx_enable_error_interrupts() 206 qat_misc_write_4(sc, RICPPINTCTL_C3XXX, RICPP_EN_C3XXX); in qat_c3xxx_enable_error_interrupts() 209 qat_misc_write_4(sc, TICPPINTCTL_C3XXX, TICPP_EN_C3XXX); in qat_c3xxx_enable_error_interrupts() 212 qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_C3XXX, CPP_CFC_UE_C3XXX); in qat_c3xxx_enable_error_interrupts() 219 qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_C3XXX | ERRMSK0_CERR_C3XXX); in qat_c3xxx_disable_error_interrupts() 223 qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_C3XXX); in qat_c3xxx_disable_error_interrupts() [all …]
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| H A D | qatvar.h | 861 qat_misc_write_4(struct qat_softc *sc, bus_size_t offset, uint32_t value) in qat_misc_write_4() function 882 qat_misc_write_4(sc, offset, reg); in qat_misc_read_write_or_4() 893 qat_misc_write_4(sc, offset, reg); in qat_misc_read_write_and_4() 918 qat_misc_write_4(sc, sc->sc_hw.qhw_ae_local_offset + offset, in qat_ae_local_write_4() 939 qat_misc_write_4(sc, sc->sc_hw.qhw_ae_offset + offset, value); in qat_ae_xfer_write_4() 946 qat_misc_write_4(sc, sc->sc_hw.qhw_cap_global_offset + offset, value); in qat_cap_global_write_4()
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| H A D | qat_hw17.c | 120 qat_misc_write_4(sc, ADMINMSGUR, addr >> 32); in qat_adm_mailbox_init() 121 qat_misc_write_4(sc, ADMINMSGLR, addr); in qat_adm_mailbox_init() 145 qat_misc_write_4(sc, mb_offset, 1); in qat_adm_mailbox_put_msg_sync() 309 qat_misc_write_4(sc, SSMWDT(i), timer); in qat_set_ssm_wdtimer() 310 qat_misc_write_4(sc, SSMWDTPKE(i), timer); in qat_set_ssm_wdtimer()
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| H A D | qat_dh895xcc.c | 159 qat_misc_write_4(sc, SMIAPF0_DH895XCC, SMIA0_MASK_DH895XCC); in qat_dh895xcc_enable_intr() 160 qat_misc_write_4(sc, SMIAPF1_DH895XCC, SMIA1_MASK_DH895XCC); in qat_dh895xcc_enable_intr()
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| H A D | qat_c2xxx.c | 160 qat_misc_write_4(sc, EP_SMIA_C2XXX, EP_SMIA_MASK_C2XXX); in qat_c2xxx_enable_intr()
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