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Searched refs:isTypeDesirableForOp (Results 1 – 7 of 7) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h308 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
H A DSIISelLowering.cpp1623 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const { in isTypeDesirableForOp() function in SITargetLowering
1646 return TargetLowering::isTypeDesirableForOp(Op, VT); in isTypeDesirableForOp()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h962 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
H A DX86ISelLowering.cpp51348 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { in isTypeDesirableForOp() function in X86TargetLowering
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1291 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntBinOp()
1359 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntShiftOp()
1408 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteExtend()
1439 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteLoad()
4850 !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
5191 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
5192 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
8126 TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) { in distributeTruncateThroughAnd()
8866 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
12288 TLI.isTypeDesirableForOp(ISD::SHL, VT)) { in visitTRUNCATE()
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H A DTargetLowering.cpp1473 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
2017 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
3623 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3609 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { in isTypeDesirableForOp() function