| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepInstrInfo.td | 628 let isPredicated = 1;
644 let isPredicated = 1;
660 let isPredicated = 1;
680 let isPredicated = 1;
701 let isPredicated = 1;
720 let isPredicated = 1;
741 let isPredicated = 1;
756 let isPredicated = 1;
772 let isPredicated = 1;
786 let isPredicated = 1;
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| H A D | HexagonVLIWPacketizer.cpp | 368 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; in isNewifiable()
570 if (!HII->isPredicated(MI)) in getPredicateSense()
701 if (HII->isPredicated(PacketMI)) { in canPromoteToNewValueStore()
702 if (!HII->isPredicated(MI)) in canPromoteToNewValueStore()
926 if (!HII->isPredicated(*I)) in restrictingDepExistInPacket()
953 assert(QII->isPredicated(MI) && "Must be predicated instruction"); in getPredicatedRegister()
1207 if (HII->isPredicated(I) || HII->isPredicated(J)) in hasDeadDependence()
1247 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) in hasControlDependence()
1468 if (HII->isPredicated(I) && HII->isPredicated(J) && in isLegalToPacketizeTogether()
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| H A D | HexagonInstrFormats.td | 86 bits<1> isPredicated = 0;
87 let TSFlags{10} = isPredicated;
184 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
296 bits<1> isPredicated = 0;
297 let TSFlags{7} = isPredicated;
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| H A D | HexagonExpandCondsets.cpp | 344 if (HII->isPredicated(*DefI)) in updateKillFlags()
422 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
492 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
724 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
759 if (PredValid && HII->isPredicated(*MI)) { in getReachingDefForPred()
917 if (!HII->isPredicated(*MI)) in renameInRange()
990 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR)) in predicate()
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| H A D | HexagonInstrInfo.h | 223 bool isPredicated(const MachineInstr &MI) const override;
388 bool isPredicated(unsigned Opcode) const;
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| H A D | HexagonPeephole.cpp | 235 if (QII->isPredicated(MI)) { in runOnMachineFunction()
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| H A D | Hexagon.td | 320 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
328 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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| H A D | HexagonInstrInfo.cpp | 611 if (Term != MBB.end() && isPredicated(*Term) && in insertBranch()
1580 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in HexagonInstrInfo
2163 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI))) in isDotNewInst()
2447 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode); in isNewValueJump()
2470 assert(isPredicated(MI)); in isPredicatedNew()
2476 assert(isPredicated(Opcode)); in isPredicatedNew()
2494 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated() function in HexagonInstrInfo
3177 if (Cond.empty() || !isPredicated(Cond[0].getImm())) in predOpcodeHasNot()
3242 if (isPredicated(MI)) { in getBaseAndOffsetPosition()
3767 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form in getDotOldOp()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
213 CantAnalyze = !isPredicated(*I); in analyzeBranch()
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) || in analyzeBranch()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CriticalAntiDepBreaker.cpp | 178 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
253 if (!TII->isPredicated(MI)) { in ScanInstruction()
608 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
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| H A D | IfConversion.cpp | 1110 bool isPredicated = TII->isPredicated(MI); in ScanInstructions() local
1122 if (!isPredicated) { in ScanInstructions()
1137 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1992 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); in IfConvertDiamondCommon()
1993 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); in IfConvertDiamondCommon()
2084 if (TI != BBI.BB->end() && TII->isPredicated(*TI)) in IfConvertDiamond()
2142 if (I.isDebugInstr() || TII->isPredicated(I)) in PredicateBlock()
2202 if (!TII->isPredicated(I) && !MI->isDebugInstr()) { in CopyAndPredicateBlock()
2256 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromTI)) in MergeBlocks()
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| H A D | TargetSchedule.cpp | 306 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) in computeOutputLatency()
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| H A D | AggressiveAntiDepBreaker.cpp | 381 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
459 TII->isPredicated(MI) || MI.isInlineAsm(); in ScanInstruction()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 865 bool isPredicated = isVectorPredicated(&MI); in producesFalseLanesZero() local
869 return isPredicated; in producesFalseLanesZero()
893 if (MO.isUse() && isPredicated) in producesFalseLanesZero()
937 bool isPredicated = isVectorPredicated(&MI); in ValidateLiveOuts() local
941 if (isPredicated) in ValidateLiveOuts()
947 else if (!isPredicated && retainsOrReduces) in ValidateLiveOuts()
949 else if (!isPredicated) in ValidateLiveOuts()
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| H A D | ARMBaseInstrInfo.cpp | 404 if (!isPredicated(*I) && in analyzeBranch()
433 if (AllowModify && !isPredicated(MBB.back()) && in analyzeBranch()
2987 isPredicated(*PotentialAND)) in optimizeCompareInstr()
3106 if (isPredicated(*MI)) in optimizeCompareInstr()
3253 if (isPredicated(MI)) in shouldSink()
4921 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
4926 if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) && in getExecutionDomain()
5020 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); in setExecutionDomain()
5042 assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); in setExecutionDomain()
6128 if (isPredicated(MI)) in getOutliningType()
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| H A D | ARMSchedule.td | 155 "ARM_MC::isPredicated",
156 "isPredicated"
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| H A D | ARMSLSHardening.cpp | 119 assert(!TII->isPredicated(MI)); in hardenReturnsAndBRs()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.h | 275 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
327 bool isPredicated() const;
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| H A D | HexagonMCChecker.cpp | 68 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { in initReg()
435 if (std::get<2>(Producer).isPredicated() && in checkNewValues()
436 (!Consumer.isPredicated() || in checkNewValues()
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| H A D | HexagonMCInstrInfo.cpp | 35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { in isPredicated() function in HexagonMCInstrInfo::PredicateInfo
718 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, in isPredicated() function in HexagonMCInstrInfo
927 if (!isPredicated(MCII, MCI)) in predicateInfo()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 46 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 180 bool isPredicated(const MachineInstr &MI) const override;
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| H A D | R600Packetizer.cpp | 79 if (TII->isPredicated(*BI)) in getPreviousVector()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 1071 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) { in analyzeInterleaving()
1173 if ((isPredicated(BlockA) || isPredicated(BlockB)) && in analyzeInterleaving()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanTransforms.cpp | 113 if (!RepR || !RepR->isPredicated()) in sinkScalarOperands()
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